2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
4 * Author: Shlomi Gridish
6 * Description: UCC GETH Driver -- PHY handling
8 * Based on 8260_io/fcc_enet.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
20 #include "asm/errno.h"
21 #include "asm/immap_qe.h"
29 #if defined(CONFIG_QE)
31 #define UEC_VERBOSE_DEBUG
32 #define ugphy_printk(format, arg...) \
33 printf(format "\n", ## arg)
35 #define ugphy_dbg(format, arg...) \
36 ugphy_printk(format , ## arg)
37 #define ugphy_err(format, arg...) \
38 ugphy_printk(format , ## arg)
39 #define ugphy_info(format, arg...) \
40 ugphy_printk(format , ## arg)
41 #define ugphy_warn(format, arg...) \
42 ugphy_printk(format , ## arg)
44 #ifdef UEC_VERBOSE_DEBUG
45 #define ugphy_vdbg ugphy_dbg
47 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
48 #endif /* UEC_VERBOSE_DEBUG */
50 static void config_genmii_advert(struct uec_mii_info *mii_info);
51 static void genmii_setup_forced(struct uec_mii_info *mii_info);
52 static void genmii_restart_aneg(struct uec_mii_info *mii_info);
53 static int gbit_config_aneg(struct uec_mii_info *mii_info);
54 static int genmii_config_aneg(struct uec_mii_info *mii_info);
55 static int genmii_update_link(struct uec_mii_info *mii_info);
56 static int genmii_read_status(struct uec_mii_info *mii_info);
57 u16 phy_read(struct uec_mii_info *mii_info, u16 regnum);
58 void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
60 /* Write value to the PHY for this device to the register at regnum, */
61 /* waiting until the write is done before it returns. All PHY */
62 /* configuration has to be done through the TSEC1 MIIM regs */
63 void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value)
65 uec_private_t *ugeth = (uec_private_t *)dev->priv;
67 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
70 ug_regs = ugeth->uec_regs;
72 /* Stop the MII management read cycle */
73 out_be32(&ug_regs->miimcom, 0);
74 /* Setting up the MII Mangement Address Register */
75 tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
76 out_be32(&ug_regs->miimadd, tmp_reg);
78 /* Setting up the MII Mangement Control Register with the value */
79 out_be32(&ug_regs->miimcon, (u32)value);
81 /* Wait till MII management write is complete */
82 while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY);
87 /* Reads from register regnum in the PHY for device dev, */
88 /* returning the value. Clears miimcom first. All PHY */
89 /* configuration has to be done through the TSEC1 MIIM regs */
90 int read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
92 uec_private_t *ugeth = (uec_private_t *)dev->priv;
94 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
98 ug_regs = ugeth->uec_regs;
100 /* Setting up the MII Mangement Address Register */
101 tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ;
102 out_be32(&ug_regs->miimadd, tmp_reg);
104 /* Perform an MII management read cycle */
105 out_be32(&ug_regs->miimcom, 0);
106 out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
108 /* Wait till MII management write is complete */
109 while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY));
113 /* Read MII management status */
114 value = (u16)in_be32(&ug_regs->miimstat);
116 ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
117 mii_id, mii_reg, (u32) &(ug_regs->miimcfg));
122 void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
124 if(mii_info->phyinfo->ack_interrupt)
125 mii_info->phyinfo->ack_interrupt(mii_info);
128 void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts)
130 mii_info->interrupts = interrupts;
131 if(mii_info->phyinfo->config_intr)
132 mii_info->phyinfo->config_intr(mii_info);
135 /* Writes MII_ADVERTISE with the appropriate values, after
136 * sanitizing advertise to make sure only supported features
139 static void config_genmii_advert(struct uec_mii_info *mii_info)
144 /* Only allow advertising what this PHY supports */
145 mii_info->advertising &= mii_info->phyinfo->features;
146 advertise = mii_info->advertising;
148 /* Setup standard advertisement */
149 adv = phy_read(mii_info, PHY_ANAR);
150 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
151 if (advertise & ADVERTISED_10baseT_Half)
152 adv |= ADVERTISE_10HALF;
153 if (advertise & ADVERTISED_10baseT_Full)
154 adv |= ADVERTISE_10FULL;
155 if (advertise & ADVERTISED_100baseT_Half)
156 adv |= ADVERTISE_100HALF;
157 if (advertise & ADVERTISED_100baseT_Full)
158 adv |= ADVERTISE_100FULL;
159 phy_write(mii_info, PHY_ANAR, adv);
162 static void genmii_setup_forced(struct uec_mii_info *mii_info)
165 u32 features = mii_info->phyinfo->features;
167 ctrl = phy_read(mii_info, PHY_BMCR);
169 ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS|
170 PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON);
171 ctrl |= PHY_BMCR_RESET;
173 switch(mii_info->speed) {
175 if(features & (SUPPORTED_1000baseT_Half
176 | SUPPORTED_1000baseT_Full)) {
177 ctrl |= PHY_BMCR_1000_MBPS;
180 mii_info->speed = SPEED_100;
182 if (features & (SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full)) {
184 ctrl |= PHY_BMCR_100_MBPS;
187 mii_info->speed = SPEED_10;
189 if (features & (SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full))
192 default: /* Unsupported speed! */
193 ugphy_err("%s: Bad speed!", mii_info->dev->name);
197 phy_write(mii_info, PHY_BMCR, ctrl);
200 /* Enable and Restart Autonegotiation */
201 static void genmii_restart_aneg(struct uec_mii_info *mii_info)
205 ctl = phy_read(mii_info, PHY_BMCR);
206 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
207 phy_write(mii_info, PHY_BMCR, ctl);
210 static int gbit_config_aneg(struct uec_mii_info *mii_info)
215 if(mii_info->autoneg) {
216 /* Configure the ADVERTISE register */
217 config_genmii_advert(mii_info);
218 advertise = mii_info->advertising;
220 adv = phy_read(mii_info, MII_1000BASETCONTROL);
221 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
222 MII_1000BASETCONTROL_HALFDUPLEXCAP);
223 if (advertise & SUPPORTED_1000baseT_Half)
224 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
225 if (advertise & SUPPORTED_1000baseT_Full)
226 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
227 phy_write(mii_info, MII_1000BASETCONTROL, adv);
229 /* Start/Restart aneg */
230 genmii_restart_aneg(mii_info);
232 genmii_setup_forced(mii_info);
237 static int marvell_config_aneg(struct uec_mii_info *mii_info)
239 /* The Marvell PHY has an errata which requires
240 * that certain registers get written in order
241 * to restart autonegotiation */
242 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
244 phy_write(mii_info, 0x1d, 0x1f);
245 phy_write(mii_info, 0x1e, 0x200c);
246 phy_write(mii_info, 0x1d, 0x5);
247 phy_write(mii_info, 0x1e, 0);
248 phy_write(mii_info, 0x1e, 0x100);
250 gbit_config_aneg(mii_info);
255 static int genmii_config_aneg(struct uec_mii_info *mii_info)
257 if (mii_info->autoneg) {
258 config_genmii_advert(mii_info);
259 genmii_restart_aneg(mii_info);
261 genmii_setup_forced(mii_info);
266 static int genmii_update_link(struct uec_mii_info *mii_info)
271 phy_read(mii_info, PHY_BMSR);
273 /* Read link and autonegotiation status */
274 status = phy_read(mii_info, PHY_BMSR);
275 if ((status & PHY_BMSR_LS) == 0)
280 /* If we are autonegotiating, and not done,
282 if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP))
288 static int genmii_read_status(struct uec_mii_info *mii_info)
293 /* Update the link, but return if there
295 err = genmii_update_link(mii_info);
299 if (mii_info->autoneg) {
300 status = phy_read(mii_info, PHY_ANLPAR);
302 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
303 mii_info->duplex = DUPLEX_FULL;
305 mii_info->duplex = DUPLEX_HALF;
306 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
307 mii_info->speed = SPEED_100;
309 mii_info->speed = SPEED_10;
312 /* On non-aneg, we assume what we put in BMCR is the speed,
313 * though magic-aneg shouldn't prevent this case from occurring
319 static int marvell_read_status(struct uec_mii_info *mii_info)
324 /* Update the link, but return if there
326 err = genmii_update_link(mii_info);
330 /* If the link is up, read the speed and duplex */
331 /* If we aren't autonegotiating, assume speeds
333 if (mii_info->autoneg && mii_info->link) {
335 status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
337 /* Get the duplexity */
338 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
339 mii_info->duplex = DUPLEX_FULL;
341 mii_info->duplex = DUPLEX_HALF;
344 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
346 case MII_M1011_PHY_SPEC_STATUS_1000:
347 mii_info->speed = SPEED_1000;
349 case MII_M1011_PHY_SPEC_STATUS_100:
350 mii_info->speed = SPEED_100;
353 mii_info->speed = SPEED_10;
362 static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
364 /* Clear the interrupts by reading the reg */
365 phy_read(mii_info, MII_M1011_IEVENT);
370 static int marvell_config_intr(struct uec_mii_info *mii_info)
372 if(mii_info->interrupts == MII_INTERRUPT_ENABLED)
373 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
375 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
380 static int dm9161_init(struct uec_mii_info *mii_info)
383 phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) |
385 /* PHY and MAC connect*/
386 phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) &
388 #ifdef CONFIG_RMII_MODE
389 phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
391 phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
393 config_genmii_advert(mii_info);
394 /* Start/restart aneg */
395 genmii_config_aneg(mii_info);
396 /* Delay to wait the aneg compeleted */
402 static int dm9161_config_aneg(struct uec_mii_info *mii_info)
407 static int dm9161_read_status(struct uec_mii_info *mii_info)
412 /* Update the link, but return if there was an error*/
413 err = genmii_update_link(mii_info);
416 /* If the link is up, read the speed and duplex
417 If we aren't autonegotiating assume speeds are as set */
418 if (mii_info->autoneg && mii_info->link) {
419 status = phy_read(mii_info, MII_DM9161_SCSR);
420 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
421 mii_info->speed = SPEED_100;
423 mii_info->speed = SPEED_10;
425 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
426 mii_info->duplex = DUPLEX_FULL;
428 mii_info->duplex = DUPLEX_HALF;
434 static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
436 /* Clear the interrupt by reading the reg */
437 phy_read(mii_info, MII_DM9161_INTR);
442 static int dm9161_config_intr(struct uec_mii_info *mii_info)
444 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
445 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
447 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
452 static void dm9161_close(struct uec_mii_info *mii_info)
456 static struct phy_info phy_info_dm9161 = {
457 .phy_id = 0x0181b880,
458 .phy_id_mask = 0x0ffffff0,
459 .name = "Davicom DM9161E",
461 .config_aneg = dm9161_config_aneg,
462 .read_status = dm9161_read_status,
463 .close = dm9161_close,
466 static struct phy_info phy_info_dm9161a = {
467 .phy_id = 0x0181b8a0,
468 .phy_id_mask = 0x0ffffff0,
469 .name = "Davicom DM9161A",
470 .features = MII_BASIC_FEATURES,
472 .config_aneg = dm9161_config_aneg,
473 .read_status = dm9161_read_status,
474 .ack_interrupt = dm9161_ack_interrupt,
475 .config_intr = dm9161_config_intr,
476 .close = dm9161_close,
479 static struct phy_info phy_info_marvell = {
480 .phy_id = 0x01410c00,
481 .phy_id_mask = 0xffffff00,
482 .name = "Marvell 88E11x1",
483 .features = MII_GBIT_FEATURES,
484 .config_aneg = &marvell_config_aneg,
485 .read_status = &marvell_read_status,
486 .ack_interrupt = &marvell_ack_interrupt,
487 .config_intr = &marvell_config_intr,
490 static struct phy_info phy_info_genmii= {
491 .phy_id = 0x00000000,
492 .phy_id_mask = 0x00000000,
493 .name = "Generic MII",
494 .features = MII_BASIC_FEATURES,
495 .config_aneg = genmii_config_aneg,
496 .read_status = genmii_read_status,
499 static struct phy_info *phy_info[] = {
507 u16 phy_read(struct uec_mii_info *mii_info, u16 regnum)
509 return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
512 void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
514 mii_info->mdio_write(mii_info->dev,
519 /* Use the PHY ID registers to determine what type of PHY is attached
520 * to device dev. return a struct phy_info structure describing that PHY
522 struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
527 struct phy_info *theInfo = NULL;
529 /* Grab the bits from PHYIR1, and put them in the upper half */
530 phy_reg = phy_read(mii_info, PHY_PHYIDR1);
531 phy_ID = (phy_reg & 0xffff) << 16;
533 /* Grab the bits from PHYIR2, and put them in the lower half */
534 phy_reg = phy_read(mii_info, PHY_PHYIDR2);
535 phy_ID |= (phy_reg & 0xffff);
537 /* loop through all the known PHY types, and find one that */
538 /* matches the ID we read from the PHY. */
539 for (i = 0; phy_info[i]; i++)
540 if (phy_info[i]->phy_id ==
541 (phy_ID & phy_info[i]->phy_id_mask)) {
542 theInfo = phy_info[i];
546 /* This shouldn't happen, as we have generic PHY support */
547 if (theInfo == NULL) {
548 ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
551 ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
557 void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
559 uec_private_t *uec = (uec_private_t *)dev->priv;
560 struct uec_mii_info *mii_info;
562 if (!uec->mii_info) {
563 printf("%s: the PHY not intialized\n", __FUNCTION__);
566 mii_info = uec->mii_info;
568 if (mode == ENET_100_RGMII) {
569 phy_write(mii_info, 0x00, 0x9140);
570 phy_write(mii_info, 0x1d, 0x001f);
571 phy_write(mii_info, 0x1e, 0x200c);
572 phy_write(mii_info, 0x1d, 0x0005);
573 phy_write(mii_info, 0x1e, 0x0000);
574 phy_write(mii_info, 0x1e, 0x0100);
575 phy_write(mii_info, 0x09, 0x0e00);
576 phy_write(mii_info, 0x04, 0x01e1);
577 phy_write(mii_info, 0x00, 0x9140);
578 phy_write(mii_info, 0x00, 0x1000);
580 phy_write(mii_info, 0x00, 0x2900);
581 phy_write(mii_info, 0x14, 0x0cd2);
582 phy_write(mii_info, 0x00, 0xa100);
583 phy_write(mii_info, 0x09, 0x0000);
584 phy_write(mii_info, 0x1b, 0x800b);
585 phy_write(mii_info, 0x04, 0x05e1);
586 phy_write(mii_info, 0x00, 0xa100);
587 phy_write(mii_info, 0x00, 0x2100);
589 } else if (mode == ENET_10_RGMII) {
590 phy_write(mii_info, 0x14, 0x8e40);
591 phy_write(mii_info, 0x1b, 0x800b);
592 phy_write(mii_info, 0x14, 0x0c82);
593 phy_write(mii_info, 0x00, 0x8100);
598 void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
600 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
601 marvell_phy_interface_mode(dev, mode);
604 #endif /* CONFIG_QE */