2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
4 * Author: Shlomi Gridish
6 * Description: UCC GETH Driver -- PHY handling
8 * Based on 8260_io/fcc_enet.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
20 #include "asm/errno.h"
21 #include "asm/immap_qe.h"
29 #define ugphy_printk(format, arg...) \
30 printf(format "\n", ## arg)
32 #define ugphy_dbg(format, arg...) \
33 ugphy_printk(format , ## arg)
34 #define ugphy_err(format, arg...) \
35 ugphy_printk(format , ## arg)
36 #define ugphy_info(format, arg...) \
37 ugphy_printk(format , ## arg)
38 #define ugphy_warn(format, arg...) \
39 ugphy_printk(format , ## arg)
41 #ifdef UEC_VERBOSE_DEBUG
42 #define ugphy_vdbg ugphy_dbg
44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
45 #endif /* UEC_VERBOSE_DEBUG */
47 /*--------------------------------------------------------------------+
48 * Fixed PHY (PHY-less) support for Ethernet Ports.
50 * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
51 *--------------------------------------------------------------------*/
54 * Some boards do not have a PHY for each ethernet port. These ports are known
55 * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
56 * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
57 * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
58 * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
59 * speed and duplex should be for the port.
61 * Example board header configuration file:
62 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
63 * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
65 * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
66 * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
67 * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
68 * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
70 * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
71 * {name, speed, duplex},
73 * #define CONFIG_SYS_FIXED_PHY_PORTS \
74 * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC0",SPEED_100,DUPLEX_FULL) \
75 * CONFIG_SYS_FIXED_PHY_PORT("FSL UEC2",SPEED_100,DUPLEX_HALF)
78 #ifndef CONFIG_FIXED_PHY
79 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
83 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
86 struct fixed_phy_port {
87 char name[NAMESIZE]; /* ethernet port name */
88 unsigned int speed; /* specified speed 10,100 or 1000 */
89 unsigned int duplex; /* specified duplex FULL or HALF */
92 static const struct fixed_phy_port fixed_phy_port[] = {
93 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
96 static void config_genmii_advert (struct uec_mii_info *mii_info);
97 static void genmii_setup_forced (struct uec_mii_info *mii_info);
98 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
99 static int gbit_config_aneg (struct uec_mii_info *mii_info);
100 static int genmii_config_aneg (struct uec_mii_info *mii_info);
101 static int genmii_update_link (struct uec_mii_info *mii_info);
102 static int genmii_read_status (struct uec_mii_info *mii_info);
103 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
104 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
106 /* Write value to the PHY for this device to the register at regnum, */
107 /* waiting until the write is done before it returns. All PHY */
108 /* configuration has to be done through the TSEC1 MIIM regs */
109 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
111 uec_private_t *ugeth = (uec_private_t *) dev->priv;
113 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
116 ug_regs = ugeth->uec_mii_regs;
118 /* Stop the MII management read cycle */
119 out_be32 (&ug_regs->miimcom, 0);
120 /* Setting up the MII Mangement Address Register */
121 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
122 out_be32 (&ug_regs->miimadd, tmp_reg);
124 /* Setting up the MII Mangement Control Register with the value */
125 out_be32 (&ug_regs->miimcon, (u32) value);
128 /* Wait till MII management write is complete */
129 while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
132 /* Reads from register regnum in the PHY for device dev, */
133 /* returning the value. Clears miimcom first. All PHY */
134 /* configuration has to be done through the TSEC1 MIIM regs */
135 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
137 uec_private_t *ugeth = (uec_private_t *) dev->priv;
139 enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
143 ug_regs = ugeth->uec_mii_regs;
145 /* Setting up the MII Mangement Address Register */
146 tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
147 out_be32 (&ug_regs->miimadd, tmp_reg);
149 /* clear MII management command cycle */
150 out_be32 (&ug_regs->miimcom, 0);
153 /* Perform an MII management read cycle */
154 out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
156 /* Wait till MII management write is complete */
157 while ((in_be32 (&ug_regs->miimind)) &
158 (MIIMIND_NOT_VALID | MIIMIND_BUSY));
160 /* Read MII management status */
161 value = (u16) in_be32 (&ug_regs->miimstat);
164 ("read wrong value : mii_id %d,mii_reg %d, base %08x",
165 mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
170 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
172 if (mii_info->phyinfo->ack_interrupt)
173 mii_info->phyinfo->ack_interrupt (mii_info);
176 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
179 mii_info->interrupts = interrupts;
180 if (mii_info->phyinfo->config_intr)
181 mii_info->phyinfo->config_intr (mii_info);
184 /* Writes MII_ADVERTISE with the appropriate values, after
185 * sanitizing advertise to make sure only supported features
188 static void config_genmii_advert (struct uec_mii_info *mii_info)
193 /* Only allow advertising what this PHY supports */
194 mii_info->advertising &= mii_info->phyinfo->features;
195 advertise = mii_info->advertising;
197 /* Setup standard advertisement */
198 adv = phy_read (mii_info, PHY_ANAR);
199 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
200 if (advertise & ADVERTISED_10baseT_Half)
201 adv |= ADVERTISE_10HALF;
202 if (advertise & ADVERTISED_10baseT_Full)
203 adv |= ADVERTISE_10FULL;
204 if (advertise & ADVERTISED_100baseT_Half)
205 adv |= ADVERTISE_100HALF;
206 if (advertise & ADVERTISED_100baseT_Full)
207 adv |= ADVERTISE_100FULL;
208 phy_write (mii_info, PHY_ANAR, adv);
211 static void genmii_setup_forced (struct uec_mii_info *mii_info)
214 u32 features = mii_info->phyinfo->features;
216 ctrl = phy_read (mii_info, PHY_BMCR);
218 ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
219 PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
220 ctrl |= PHY_BMCR_RESET;
222 switch (mii_info->speed) {
224 if (features & (SUPPORTED_1000baseT_Half
225 | SUPPORTED_1000baseT_Full)) {
226 ctrl |= PHY_BMCR_1000_MBPS;
229 mii_info->speed = SPEED_100;
231 if (features & (SUPPORTED_100baseT_Half
232 | SUPPORTED_100baseT_Full)) {
233 ctrl |= PHY_BMCR_100_MBPS;
236 mii_info->speed = SPEED_10;
238 if (features & (SUPPORTED_10baseT_Half
239 | SUPPORTED_10baseT_Full))
241 default: /* Unsupported speed! */
242 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
246 phy_write (mii_info, PHY_BMCR, ctrl);
249 /* Enable and Restart Autonegotiation */
250 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
254 ctl = phy_read (mii_info, PHY_BMCR);
255 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
256 phy_write (mii_info, PHY_BMCR, ctl);
259 static int gbit_config_aneg (struct uec_mii_info *mii_info)
264 if (mii_info->autoneg) {
265 /* Configure the ADVERTISE register */
266 config_genmii_advert (mii_info);
267 advertise = mii_info->advertising;
269 adv = phy_read (mii_info, MII_1000BASETCONTROL);
270 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
271 MII_1000BASETCONTROL_HALFDUPLEXCAP);
272 if (advertise & SUPPORTED_1000baseT_Half)
273 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
274 if (advertise & SUPPORTED_1000baseT_Full)
275 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
276 phy_write (mii_info, MII_1000BASETCONTROL, adv);
278 /* Start/Restart aneg */
279 genmii_restart_aneg (mii_info);
281 genmii_setup_forced (mii_info);
286 static int marvell_config_aneg (struct uec_mii_info *mii_info)
288 /* The Marvell PHY has an errata which requires
289 * that certain registers get written in order
290 * to restart autonegotiation */
291 phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
293 phy_write (mii_info, 0x1d, 0x1f);
294 phy_write (mii_info, 0x1e, 0x200c);
295 phy_write (mii_info, 0x1d, 0x5);
296 phy_write (mii_info, 0x1e, 0);
297 phy_write (mii_info, 0x1e, 0x100);
299 gbit_config_aneg (mii_info);
304 static int genmii_config_aneg (struct uec_mii_info *mii_info)
306 if (mii_info->autoneg) {
307 config_genmii_advert (mii_info);
308 genmii_restart_aneg (mii_info);
310 genmii_setup_forced (mii_info);
315 static int genmii_update_link (struct uec_mii_info *mii_info)
319 /* Status is read once to clear old link state */
320 phy_read (mii_info, PHY_BMSR);
323 * Wait if the link is up, and autonegotiation is in progress
324 * (ie - we're capable and it's not done)
326 status = phy_read(mii_info, PHY_BMSR);
327 if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
328 && !(status & PHY_BMSR_AUTN_COMP)) {
331 while (!(status & PHY_BMSR_AUTN_COMP)) {
335 if (i > UGETH_AN_TIMEOUT) {
341 udelay(1000); /* 1 ms */
342 status = phy_read(mii_info, PHY_BMSR);
345 udelay(500000); /* another 500 ms (results in faster booting) */
347 if (status & PHY_BMSR_LS)
356 static int genmii_read_status (struct uec_mii_info *mii_info)
361 /* Update the link, but return if there
363 err = genmii_update_link (mii_info);
367 if (mii_info->autoneg) {
368 status = phy_read(mii_info, MII_1000BASETSTATUS);
370 if (status & (LPA_1000FULL | LPA_1000HALF)) {
371 mii_info->speed = SPEED_1000;
372 if (status & LPA_1000FULL)
373 mii_info->duplex = DUPLEX_FULL;
375 mii_info->duplex = DUPLEX_HALF;
377 status = phy_read(mii_info, PHY_ANLPAR);
379 if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
380 mii_info->duplex = DUPLEX_FULL;
382 mii_info->duplex = DUPLEX_HALF;
383 if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
384 mii_info->speed = SPEED_100;
386 mii_info->speed = SPEED_10;
390 /* On non-aneg, we assume what we put in BMCR is the speed,
391 * though magic-aneg shouldn't prevent this case from occurring
397 static int bcm_init(struct uec_mii_info *mii_info)
399 struct eth_device *edev = mii_info->dev;
400 uec_private_t *uec = edev->priv;
402 gbit_config_aneg(mii_info);
404 if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
405 (uec->uec_info->speed == 1000)) {
409 /* Wait for aneg to complete. */
411 val = phy_read(mii_info, PHY_BMSR);
412 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
414 /* Set RDX clk delay. */
415 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
417 val = phy_read(mii_info, 0x18);
418 /* Set RDX-RXC skew. */
420 val |= (7 | (7 << 12));
421 /* Write bits 14:0. */
423 phy_write(mii_info, 0x18, val);
429 static int marvell_init(struct uec_mii_info *mii_info)
431 struct eth_device *edev = mii_info->dev;
432 uec_private_t *uec = edev->priv;
433 enum enet_interface_type iface = uec->uec_info->enet_interface_type;
434 int speed = uec->uec_info->speed;
436 if ((speed == 1000) &&
437 (iface == RGMII_ID ||
438 iface == RGMII_RXID ||
439 iface == RGMII_TXID)) {
442 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
443 if (iface == RGMII_ID) {
444 temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
445 } else if (iface == RGMII_RXID) {
446 temp &= ~MII_M1111_TX_DELAY;
447 temp |= MII_M1111_RX_DELAY;
448 } else if (iface == RGMII_TXID) {
449 temp &= ~MII_M1111_RX_DELAY;
450 temp |= MII_M1111_TX_DELAY;
452 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
454 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
455 temp &= ~MII_M1111_HWCFG_MODE_MASK;
456 temp |= MII_M1111_HWCFG_MODE_RGMII;
457 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
459 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
465 static int marvell_read_status (struct uec_mii_info *mii_info)
470 /* Update the link, but return if there
472 err = genmii_update_link (mii_info);
476 /* If the link is up, read the speed and duplex */
477 /* If we aren't autonegotiating, assume speeds
479 if (mii_info->autoneg && mii_info->link) {
482 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
484 /* Get the duplexity */
485 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
486 mii_info->duplex = DUPLEX_FULL;
488 mii_info->duplex = DUPLEX_HALF;
491 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
493 case MII_M1011_PHY_SPEC_STATUS_1000:
494 mii_info->speed = SPEED_1000;
496 case MII_M1011_PHY_SPEC_STATUS_100:
497 mii_info->speed = SPEED_100;
500 mii_info->speed = SPEED_10;
509 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
511 /* Clear the interrupts by reading the reg */
512 phy_read (mii_info, MII_M1011_IEVENT);
517 static int marvell_config_intr (struct uec_mii_info *mii_info)
519 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
520 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
522 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
527 static int dm9161_init (struct uec_mii_info *mii_info)
530 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
532 /* PHY and MAC connect */
533 phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
536 phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
538 config_genmii_advert (mii_info);
539 /* Start/restart aneg */
540 genmii_config_aneg (mii_info);
545 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
550 static int dm9161_read_status (struct uec_mii_info *mii_info)
555 /* Update the link, but return if there was an error */
556 err = genmii_update_link (mii_info);
559 /* If the link is up, read the speed and duplex
560 If we aren't autonegotiating assume speeds are as set */
561 if (mii_info->autoneg && mii_info->link) {
562 status = phy_read (mii_info, MII_DM9161_SCSR);
563 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
564 mii_info->speed = SPEED_100;
566 mii_info->speed = SPEED_10;
568 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
569 mii_info->duplex = DUPLEX_FULL;
571 mii_info->duplex = DUPLEX_HALF;
577 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
579 /* Clear the interrupt by reading the reg */
580 phy_read (mii_info, MII_DM9161_INTR);
585 static int dm9161_config_intr (struct uec_mii_info *mii_info)
587 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
588 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
590 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
595 static void dm9161_close (struct uec_mii_info *mii_info)
599 static int fixed_phy_aneg (struct uec_mii_info *mii_info)
601 mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
605 static int fixed_phy_read_status (struct uec_mii_info *mii_info)
609 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
610 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
611 strlen(mii_info->dev->name)) == 0) {
612 mii_info->speed = fixed_phy_port[i].speed;
613 mii_info->duplex = fixed_phy_port[i].duplex;
614 mii_info->link = 1; /* Link is always UP */
622 static int smsc_config_aneg (struct uec_mii_info *mii_info)
627 static int smsc_read_status (struct uec_mii_info *mii_info)
632 /* Update the link, but return if there
634 err = genmii_update_link (mii_info);
638 /* If the link is up, read the speed and duplex */
639 /* If we aren't autonegotiating, assume speeds
641 if (mii_info->autoneg && mii_info->link) {
644 status = phy_read (mii_info, 0x1f);
645 val = (status & 0x1c) >> 2;
649 mii_info->duplex = DUPLEX_HALF;
650 mii_info->speed = SPEED_10;
653 mii_info->duplex = DUPLEX_FULL;
654 mii_info->speed = SPEED_10;
657 mii_info->duplex = DUPLEX_HALF;
658 mii_info->speed = SPEED_100;
661 mii_info->duplex = DUPLEX_FULL;
662 mii_info->speed = SPEED_100;
671 static struct phy_info phy_info_dm9161 = {
672 .phy_id = 0x0181b880,
673 .phy_id_mask = 0x0ffffff0,
674 .name = "Davicom DM9161E",
676 .config_aneg = dm9161_config_aneg,
677 .read_status = dm9161_read_status,
678 .close = dm9161_close,
681 static struct phy_info phy_info_dm9161a = {
682 .phy_id = 0x0181b8a0,
683 .phy_id_mask = 0x0ffffff0,
684 .name = "Davicom DM9161A",
685 .features = MII_BASIC_FEATURES,
687 .config_aneg = dm9161_config_aneg,
688 .read_status = dm9161_read_status,
689 .ack_interrupt = dm9161_ack_interrupt,
690 .config_intr = dm9161_config_intr,
691 .close = dm9161_close,
694 static struct phy_info phy_info_marvell = {
695 .phy_id = 0x01410c00,
696 .phy_id_mask = 0xffffff00,
697 .name = "Marvell 88E11x1",
698 .features = MII_GBIT_FEATURES,
699 .init = &marvell_init,
700 .config_aneg = &marvell_config_aneg,
701 .read_status = &marvell_read_status,
702 .ack_interrupt = &marvell_ack_interrupt,
703 .config_intr = &marvell_config_intr,
706 static struct phy_info phy_info_bcm5481 = {
707 .phy_id = 0x0143bca0,
708 .phy_id_mask = 0xffffff0,
709 .name = "Broadcom 5481",
710 .features = MII_GBIT_FEATURES,
711 .read_status = genmii_read_status,
715 static struct phy_info phy_info_fixedphy = {
716 .phy_id = CONFIG_FIXED_PHY,
717 .phy_id_mask = CONFIG_FIXED_PHY,
719 .config_aneg = fixed_phy_aneg,
720 .read_status = fixed_phy_read_status,
723 static struct phy_info phy_info_smsclan8700 = {
724 .phy_id = 0x0007c0c0,
725 .phy_id_mask = 0xfffffff0,
726 .name = "SMSC LAN8700",
727 .features = MII_BASIC_FEATURES,
728 .config_aneg = smsc_config_aneg,
729 .read_status = smsc_read_status,
732 static struct phy_info phy_info_genmii = {
733 .phy_id = 0x00000000,
734 .phy_id_mask = 0x00000000,
735 .name = "Generic MII",
736 .features = MII_BASIC_FEATURES,
737 .config_aneg = genmii_config_aneg,
738 .read_status = genmii_read_status,
741 static struct phy_info *phy_info[] = {
746 &phy_info_smsclan8700,
752 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
754 return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
757 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
759 mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
762 /* Use the PHY ID registers to determine what type of PHY is attached
763 * to device dev. return a struct phy_info structure describing that PHY
765 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
770 struct phy_info *theInfo = NULL;
772 /* Grab the bits from PHYIR1, and put them in the upper half */
773 phy_reg = phy_read (mii_info, PHY_PHYIDR1);
774 phy_ID = (phy_reg & 0xffff) << 16;
776 /* Grab the bits from PHYIR2, and put them in the lower half */
777 phy_reg = phy_read (mii_info, PHY_PHYIDR2);
778 phy_ID |= (phy_reg & 0xffff);
780 /* loop through all the known PHY types, and find one that */
781 /* matches the ID we read from the PHY. */
782 for (i = 0; phy_info[i]; i++)
783 if (phy_info[i]->phy_id ==
784 (phy_ID & phy_info[i]->phy_id_mask)) {
785 theInfo = phy_info[i];
789 /* This shouldn't happen, as we have generic PHY support */
790 if (theInfo == NULL) {
791 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
794 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
800 void marvell_phy_interface_mode (struct eth_device *dev,
801 enet_interface_type_e type,
805 uec_private_t *uec = (uec_private_t *) dev->priv;
806 struct uec_mii_info *mii_info;
809 if (!uec->mii_info) {
810 printf ("%s: the PHY not initialized\n", __FUNCTION__);
813 mii_info = uec->mii_info;
817 phy_write (mii_info, 0x00, 0x9140);
818 phy_write (mii_info, 0x1d, 0x001f);
819 phy_write (mii_info, 0x1e, 0x200c);
820 phy_write (mii_info, 0x1d, 0x0005);
821 phy_write (mii_info, 0x1e, 0x0000);
822 phy_write (mii_info, 0x1e, 0x0100);
823 phy_write (mii_info, 0x09, 0x0e00);
824 phy_write (mii_info, 0x04, 0x01e1);
825 phy_write (mii_info, 0x00, 0x9140);
826 phy_write (mii_info, 0x00, 0x1000);
828 phy_write (mii_info, 0x00, 0x2900);
829 phy_write (mii_info, 0x14, 0x0cd2);
830 phy_write (mii_info, 0x00, 0xa100);
831 phy_write (mii_info, 0x09, 0x0000);
832 phy_write (mii_info, 0x1b, 0x800b);
833 phy_write (mii_info, 0x04, 0x05e1);
834 phy_write (mii_info, 0x00, 0xa100);
835 phy_write (mii_info, 0x00, 0x2100);
837 } else if (speed == 10) {
838 phy_write (mii_info, 0x14, 0x8e40);
839 phy_write (mii_info, 0x1b, 0x800b);
840 phy_write (mii_info, 0x14, 0x0c82);
841 phy_write (mii_info, 0x00, 0x8100);
846 /* handle 88e1111 rev.B2 erratum 5.6 */
847 if (mii_info->autoneg) {
848 status = phy_read (mii_info, PHY_BMCR);
849 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
851 /* now the B2 will correctly report autoneg completion status */
854 void change_phy_interface_mode (struct eth_device *dev,
855 enet_interface_type_e type, int speed)
857 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
858 marvell_phy_interface_mode (dev, type, speed);