1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
8 #include <dt-structs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cru_rk322x.h>
16 #include <asm/arch/grf_rk322x.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/sdram_rk322x.h>
19 #include <asm/arch/timer.h>
20 #include <asm/arch/uart.h>
21 #include <asm/arch/sdram_common.h>
22 #include <asm/types.h>
23 #include <linux/err.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 struct rk322x_ddr_pctl *pctl;
28 struct rk322x_ddr_phy *phy;
29 struct rk322x_service_sys *msch;
33 struct chan_info chan[1];
36 struct rk322x_cru *cru;
37 struct rk322x_grf *grf;
40 struct rk322x_sdram_params {
41 #if CONFIG_IS_ENABLED(OF_PLATDATA)
42 struct dtd_rockchip_rk3228_dmc of_plat;
44 struct rk322x_sdram_channel ch[1];
45 struct rk322x_pctl_timing pctl_timing;
46 struct rk322x_phy_timing phy_timing;
47 struct rk322x_base_params base;
52 #ifdef CONFIG_TPL_BUILD
54 * [7:6] bank(n:n bit bank)
56 * [3] cs(0:1 cs, 1:2 cs)
57 * [2:1] bank(n:n bit bank)
60 const char ddr_cfg_2_rbc[] = {
61 ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 1),
62 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 1),
63 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 1),
64 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 1),
65 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 2),
66 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 2),
67 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 2),
68 ((0 << 6) | (0 << 4) | (0 << 3) | (1 << 2) | 0),
69 ((0 << 6) | (1 << 4) | (0 << 3) | (1 << 2) | 0),
70 ((0 << 6) | (2 << 4) | (0 << 3) | (1 << 2) | 0),
71 ((0 << 6) | (3 << 4) | (0 << 3) | (1 << 2) | 0),
72 ((0 << 6) | (2 << 4) | (0 << 3) | (0 << 2) | 1),
73 ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 2),
74 ((1 << 6) | (1 << 4) | (0 << 3) | (0 << 2) | 1),
75 ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 1),
76 ((0 << 6) | (3 << 4) | (1 << 3) | (1 << 2) | 0),
79 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
83 for (i = 0; i < n / sizeof(u32); i++) {
90 void phy_pctrl_reset(struct rk322x_cru *cru,
91 struct rk322x_ddr_phy *ddr_phy)
93 rk_clrsetreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
94 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
95 1 << DDRPHY_SRST_SHIFT,
96 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
97 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
101 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
102 1 << DDRPHY_SRST_SHIFT);
105 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
106 1 << DDRCTRL_SRST_SHIFT);
109 clrbits_le32(&ddr_phy->ddrphy_reg[0],
110 SOFT_RESET_MASK << SOFT_RESET_SHIFT);
112 setbits_le32(&ddr_phy->ddrphy_reg[0],
113 SOFT_DERESET_ANALOG);
115 setbits_le32(&ddr_phy->ddrphy_reg[0],
116 SOFT_DERESET_DIGITAL);
121 void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq)
125 setbits_le32(&ddr_phy->ddrphy_reg[0x13], 0x10);
126 setbits_le32(&ddr_phy->ddrphy_reg[0x26], 0x10);
127 setbits_le32(&ddr_phy->ddrphy_reg[0x36], 0x10);
128 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x10);
129 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x10);
131 clrbits_le32(&ddr_phy->ddrphy_reg[0x14], 0x8);
132 clrbits_le32(&ddr_phy->ddrphy_reg[0x27], 0x8);
133 clrbits_le32(&ddr_phy->ddrphy_reg[0x37], 0x8);
134 clrbits_le32(&ddr_phy->ddrphy_reg[0x47], 0x8);
135 clrbits_le32(&ddr_phy->ddrphy_reg[0x57], 0x8);
138 setbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);
140 clrbits_le32(&ddr_phy->ddrphy_reg[0xa4], 0x1f);
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]);
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]);
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]);
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]);
153 static void send_command(struct rk322x_ddr_pctl *pctl,
154 u32 rank, u32 cmd, u32 arg)
156 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
158 while (readl(&pctl->mcmd) & START_CMD)
162 static void memory_init(struct chan_info *chan,
163 struct rk322x_sdram_params *sdram_params)
165 struct rk322x_ddr_pctl *pctl = chan->pctl;
166 u32 dramtype = sdram_params->base.dramtype;
168 if (dramtype == DDR3) {
169 send_command(pctl, 3, DESELECT_CMD, 0);
171 send_command(pctl, 3, PREA_CMD, 0);
172 send_command(pctl, 3, MRS_CMD,
173 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
174 (sdram_params->phy_timing.mr[2] & CMD_ADDR_MASK) <<
177 send_command(pctl, 3, MRS_CMD,
178 (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
179 (sdram_params->phy_timing.mr[3] & CMD_ADDR_MASK) <<
182 send_command(pctl, 3, MRS_CMD,
183 (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
184 (sdram_params->phy_timing.mr[1] & CMD_ADDR_MASK) <<
187 send_command(pctl, 3, MRS_CMD,
188 (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
189 ((sdram_params->phy_timing.mr[0] |
191 CMD_ADDR_MASK) << CMD_ADDR_SHIFT);
193 send_command(pctl, 3, ZQCL_CMD, 0);
195 send_command(pctl, 3, MRS_CMD,
196 (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
197 (0 & LPDDR23_OP_MASK) <<
200 send_command(pctl, 3, MRS_CMD,
201 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
202 (0xff & LPDDR23_OP_MASK) <<
205 send_command(pctl, 3, MRS_CMD,
206 (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
207 (0xff & LPDDR23_OP_MASK) <<
210 send_command(pctl, 3, MRS_CMD,
211 (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
212 (sdram_params->phy_timing.mr[1] &
213 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
214 send_command(pctl, 3, MRS_CMD,
215 (2 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
216 (sdram_params->phy_timing.mr[2] &
217 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
218 send_command(pctl, 3, MRS_CMD,
219 (3 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT |
220 (sdram_params->phy_timing.mr[3] &
221 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
222 if (dramtype == LPDDR3)
223 send_command(pctl, 3, MRS_CMD, (11 & LPDDR23_MA_MASK) <<
225 (sdram_params->phy_timing.mr11 &
226 LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT);
230 static u32 data_training(struct chan_info *chan)
232 struct rk322x_ddr_phy *ddr_phy = chan->phy;
233 struct rk322x_ddr_pctl *pctl = chan->pctl;
235 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf;
238 /* disable auto refresh */
239 value = readl(&pctl->trefi) | (1 << 31);
240 writel(1 << 31, &pctl->trefi);
242 clrsetbits_le32(&ddr_phy->ddrphy_reg[2], 0x30,
243 DQS_SQU_CAL_SEL_CS0);
244 setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START);
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]);
249 clrbits_le32(&ddr_phy->ddrphy_reg[2],
253 * since data training will take about 20us, so send some auto
254 * refresh(about 7.8us) to complement the lost time
256 send_command(pctl, 3, PREA_CMD, 0);
257 send_command(pctl, 3, REF_CMD, 0);
259 writel(value, &pctl->trefi);
264 ret = (ret & 0xf) ^ bw;
265 ret = (ret == 0) ? 0 : -1;
270 static void move_to_config_state(struct rk322x_ddr_pctl *pctl)
275 state = readl(&pctl->stat) & PCTL_STAT_MASK;
278 writel(WAKEUP_STATE, &pctl->sctl);
279 while ((readl(&pctl->stat) & PCTL_STAT_MASK)
283 * If at low power state, need wakeup first, and then
284 * enter the config, so fallthrough
289 writel(CFG_STATE, &pctl->sctl);
290 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
301 static void move_to_access_state(struct rk322x_ddr_pctl *pctl)
306 state = readl(&pctl->stat) & PCTL_STAT_MASK;
309 writel(WAKEUP_STATE, &pctl->sctl);
310 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
314 writel(CFG_STATE, &pctl->sctl);
315 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
319 writel(GO_STATE, &pctl->sctl);
320 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
331 static void move_to_lowpower_state(struct rk322x_ddr_pctl *pctl)
336 state = readl(&pctl->stat) & PCTL_STAT_MASK;
339 writel(CFG_STATE, &pctl->sctl);
340 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
344 writel(GO_STATE, &pctl->sctl);
345 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
349 writel(SLEEP_STATE, &pctl->sctl);
350 while ((readl(&pctl->stat) & PCTL_STAT_MASK) !=
362 /* pctl should in low power mode when call this function */
363 static void phy_softreset(struct dram_info *dram)
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;
366 struct rk322x_grf *grf = dram->grf;
368 writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]);
369 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2);
371 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2);
373 setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3);
374 writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]);
377 /* bw: 2: 32bit, 1:16bit */
378 static void set_bw(struct dram_info *dram, u32 bw)
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl;
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy;
382 struct rk322x_grf *grf = dram->grf;
385 setbits_le32(&pctl->ppcfg, 1);
386 clrbits_le32(&ddr_phy->ddrphy_reg[0], 0xc << 4);
387 writel(GRF_MSCH_NOC_16BIT_EN, &grf->soc_con[0]);
388 clrbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);
389 clrbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);
391 clrbits_le32(&pctl->ppcfg, 1);
392 setbits_le32(&ddr_phy->ddrphy_reg[0], 0xf << 4);
393 writel(GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN,
395 setbits_le32(&ddr_phy->ddrphy_reg[0x46], 0x8);
396 setbits_le32(&ddr_phy->ddrphy_reg[0x56], 0x8);
400 static void pctl_cfg(struct rk322x_ddr_pctl *pctl,
401 struct rk322x_sdram_params *sdram_params,
402 struct rk322x_grf *grf)
406 u32 dramtype = sdram_params->base.dramtype;
408 if (sdram_params->ch[0].bw == 2)
409 bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN;
411 bw = GRF_MSCH_NOC_16BIT_EN;
413 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
414 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
415 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
416 writel(0x51010, &pctl->dfilpcfg0);
418 writel(1, &pctl->dfitphyupdtype0);
419 writel(0x0d, &pctl->dfitphyrdlat);
420 writel(0, &pctl->dfitphywrdata);
422 writel(0, &pctl->dfiupdcfg);
423 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
424 sizeof(struct rk322x_pctl_timing));
425 if (dramtype == DDR3) {
426 writel((1 << 3) | (1 << 11),
428 writel(7 << 16, &pctl->dfiodtcfg1);
429 writel((readl(&pctl->tcl) - 1) / 2 - 1, &pctl->dfitrddataen);
430 writel((readl(&pctl->tcwl) - 1) / 2 - 1, &pctl->dfitphywrlat);
431 writel(500, &pctl->trsth);
432 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
433 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
434 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
436 writel(bw | GRF_DDR3_EN, &grf->soc_con[0]);
438 if (sdram_params->phy_timing.bl & PHT_BL_8)
439 burst_len = MDDR_LPDDR2_BL_8;
441 burst_len = MDDR_LPDDR2_BL_4;
443 writel(readl(&pctl->tcl) / 2 - 1, &pctl->dfitrddataen);
444 writel(readl(&pctl->tcwl) / 2 - 1, &pctl->dfitphywrlat);
445 writel(0, &pctl->trsth);
446 if (dramtype == LPDDR2) {
447 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
448 LPDDR2_S4 | LPDDR2_EN | burst_len |
449 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
450 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
452 writel(0, &pctl->dfiodtcfg);
453 writel(0, &pctl->dfiodtcfg1);
455 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
456 LPDDR2_S4 | LPDDR3_EN | burst_len |
457 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
458 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
460 writel((1 << 3) | (1 << 2), &pctl->dfiodtcfg);
461 writel((7 << 16) | 4, &pctl->dfiodtcfg1);
463 writel(bw | GRF_LPDDR2_3_EN, &grf->soc_con[0]);
465 setbits_le32(&pctl->scfg, 1);
468 static void phy_cfg(struct chan_info *chan,
469 struct rk322x_sdram_params *sdram_params)
471 struct rk322x_ddr_phy *ddr_phy = chan->phy;
472 struct rk322x_service_sys *axi_bus = chan->msch;
473 struct rk322x_msch_timings *noc_timing = &sdram_params->base.noc_timing;
474 struct rk322x_phy_timing *phy_timing = &sdram_params->phy_timing;
475 struct rk322x_pctl_timing *pctl_timing = &sdram_params->pctl_timing;
476 u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
478 writel(noc_timing->ddrtiming, &axi_bus->ddrtiming);
479 writel(noc_timing->ddrmode, &axi_bus->ddrmode);
480 writel(noc_timing->readlatency, &axi_bus->readlatency);
481 writel(noc_timing->activate, &axi_bus->activate);
482 writel(noc_timing->devtodev, &axi_bus->devtodev);
484 switch (sdram_params->base.dramtype) {
486 writel(PHY_DDR3 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
489 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
492 writel(PHY_LPDDR2 | phy_timing->bl, &ddr_phy->ddrphy_reg[1]);
496 writel(phy_timing->cl_al, &ddr_phy->ddrphy_reg[0xb]);
497 writel(pctl_timing->tcwl, &ddr_phy->ddrphy_reg[0xc]);
499 cmd_drv = PHY_RON_RTT_34OHM;
500 clk_drv = PHY_RON_RTT_45OHM;
501 dqs_drv = PHY_RON_RTT_34OHM;
502 if (sdram_params->base.dramtype == LPDDR2)
503 dqs_odt = PHY_RON_RTT_DISABLE;
505 dqs_odt = PHY_RON_RTT_225OHM;
507 writel(cmd_drv, &ddr_phy->ddrphy_reg[0x11]);
508 clrsetbits_le32(&ddr_phy->ddrphy_reg[0x12], (0x1f << 3), cmd_drv << 3);
509 writel(clk_drv, &ddr_phy->ddrphy_reg[0x16]);
510 writel(clk_drv, &ddr_phy->ddrphy_reg[0x18]);
512 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x20]);
513 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x2f]);
514 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x30]);
515 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x3f]);
516 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x40]);
517 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x4f]);
518 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x50]);
519 writel(dqs_drv, &ddr_phy->ddrphy_reg[0x5f]);
521 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x21]);
522 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x2e]);
523 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x31]);
524 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x3e]);
525 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x41]);
526 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x4e]);
527 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x51]);
528 writel(dqs_odt, &ddr_phy->ddrphy_reg[0x5e]);
531 void dram_cfg_rbc(struct chan_info *chan,
532 struct rk322x_sdram_params *sdram_params)
536 struct rk322x_sdram_channel *config = &sdram_params->ch[0];
537 struct rk322x_service_sys *axi_bus = chan->msch;
539 move_to_config_state(chan->pctl);
541 if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) {
542 if ((config->col + config->bw) == 12) {
545 } else if ((config->col + config->bw) == 11) {
550 noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) |
551 (config->col + config->bw - 11);
552 for (i = 0; i < 11; i++) {
553 if (noc_config == ddr_cfg_2_rbc[i])
560 noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) |
561 (config->col + config->bw - 11);
563 for (i = 11; i < 14; i++) {
564 if (noc_config == ddr_cfg_2_rbc[i])
573 writel(i, &axi_bus->ddrconf);
574 move_to_access_state(chan->pctl);
577 static void dram_all_config(const struct dram_info *dram,
578 struct rk322x_sdram_params *sdram_params)
580 struct rk322x_sdram_channel *info = &sdram_params->ch[0];
583 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
584 sys_reg |= (1 - 1) << SYS_REG_NUM_CH_SHIFT;
585 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(0);
586 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(0);
587 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(0);
588 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(0);
589 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(0);
590 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0);
591 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(0);
592 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(0);
593 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(0);
595 writel(sys_reg, &dram->grf->os_reg[2]);
598 #define TEST_PATTEN 0x5aa5f00f
600 static int dram_cap_detect(struct dram_info *dram,
601 struct rk322x_sdram_params *sdram_params)
603 u32 bw, row, col, addr;
605 struct rk322x_service_sys *axi_bus = dram->chan[0].msch;
607 if (sdram_params->base.dramtype == DDR3)
608 sdram_params->ch[0].dbw = 1;
610 sdram_params->ch[0].dbw = 2;
612 move_to_config_state(dram->chan[0].pctl);
615 if (data_training(&dram->chan[0]) == 0) {
620 move_to_lowpower_state(dram->chan[0].pctl);
622 move_to_config_state(dram->chan[0].pctl);
623 if (data_training(&dram->chan[0])) {
624 printf("BW detect error\n");
628 sdram_params->ch[0].bw = bw;
629 sdram_params->ch[0].bk = 3;
632 writel(6, &axi_bus->ddrconf);
634 writel(3, &axi_bus->ddrconf);
635 move_to_access_state(dram->chan[0].pctl);
636 for (col = 11; col >= 9; col--) {
637 writel(0, CONFIG_SYS_SDRAM_BASE);
638 addr = CONFIG_SYS_SDRAM_BASE +
639 (1 << (col + bw - 1));
640 writel(TEST_PATTEN, addr);
641 if ((readl(addr) == TEST_PATTEN) &&
642 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
646 printf("Col detect error\n");
650 sdram_params->ch[0].col = col;
653 writel(10, &axi_bus->ddrconf);
656 for (row = 16; row >= 12; row--) {
657 writel(0, CONFIG_SYS_SDRAM_BASE);
658 addr = CONFIG_SYS_SDRAM_BASE + (1u << (row + 11 + 3 - 1));
659 writel(TEST_PATTEN, addr);
660 if ((readl(addr) == TEST_PATTEN) &&
661 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
665 printf("Row detect error\n");
668 sdram_params->ch[0].cs1_row = row;
669 sdram_params->ch[0].row_3_4 = 0;
670 sdram_params->ch[0].cs0_row = row;
673 writel(0, CONFIG_SYS_SDRAM_BASE);
674 writel(TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30));
675 writel(~TEST_PATTEN, CONFIG_SYS_SDRAM_BASE + (1u << 30) + 4);
676 if ((readl(CONFIG_SYS_SDRAM_BASE + (1u << 30)) == TEST_PATTEN) &&
677 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
678 sdram_params->ch[0].rank = 2;
680 sdram_params->ch[0].rank = 1;
685 static int sdram_init(struct dram_info *dram,
686 struct rk322x_sdram_params *sdram_params)
690 ret = clk_set_rate(&dram->ddr_clk,
691 sdram_params->base.ddr_freq * MHz * 2);
693 printf("Could not set DDR clock\n");
697 phy_pctrl_reset(dram->cru, dram->chan[0].phy);
698 phy_dll_bypass_set(dram->chan[0].phy, sdram_params->base.ddr_freq);
699 pctl_cfg(dram->chan[0].pctl, sdram_params, dram->grf);
700 phy_cfg(&dram->chan[0], sdram_params);
701 writel(POWER_UP_START, &dram->chan[0].pctl->powctl);
702 while (!(readl(&dram->chan[0].pctl->powstat) & POWER_UP_DONE))
704 memory_init(&dram->chan[0], sdram_params);
705 move_to_access_state(dram->chan[0].pctl);
706 ret = dram_cap_detect(dram, sdram_params);
709 dram_cfg_rbc(&dram->chan[0], sdram_params);
710 dram_all_config(dram, sdram_params);
715 static int rk322x_dmc_ofdata_to_platdata(struct udevice *dev)
717 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
718 struct rk322x_sdram_params *params = dev_get_platdata(dev);
719 const void *blob = gd->fdt_blob;
720 int node = dev_of_offset(dev);
723 params->num_channels = 1;
725 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
726 (u32 *)¶ms->pctl_timing,
727 sizeof(params->pctl_timing) / sizeof(u32));
729 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
732 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
733 (u32 *)¶ms->phy_timing,
734 sizeof(params->phy_timing) / sizeof(u32));
736 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
739 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
740 (u32 *)¶ms->base,
741 sizeof(params->base) / sizeof(u32));
743 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
746 ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
753 #endif /* CONFIG_TPL_BUILD */
755 #if CONFIG_IS_ENABLED(OF_PLATDATA)
756 static int conv_of_platdata(struct udevice *dev)
758 struct rk322x_sdram_params *plat = dev_get_platdata(dev);
759 struct dtd_rockchip_rk322x_dmc *of_plat = &plat->of_plat;
762 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
763 sizeof(plat->pctl_timing));
764 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
765 sizeof(plat->phy_timing));
766 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
768 plat->num_channels = 1;
769 ret = regmap_init_mem_platdata(dev, of_plat->reg,
770 ARRAY_SIZE(of_plat->reg) / 2,
779 static int rk322x_dmc_probe(struct udevice *dev)
781 #ifdef CONFIG_TPL_BUILD
782 struct rk322x_sdram_params *plat = dev_get_platdata(dev);
784 struct udevice *dev_clk;
786 struct dram_info *priv = dev_get_priv(dev);
788 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
789 #ifdef CONFIG_TPL_BUILD
790 #if CONFIG_IS_ENABLED(OF_PLATDATA)
791 ret = conv_of_platdata(dev);
796 priv->chan[0].msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
797 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
798 priv->chan[0].phy = regmap_get_range(plat->map, 1);
799 ret = rockchip_get_clk(&dev_clk);
802 priv->ddr_clk.id = CLK_DDR;
803 ret = clk_request(dev_clk, &priv->ddr_clk);
807 priv->cru = rockchip_get_cru();
808 if (IS_ERR(priv->cru))
809 return PTR_ERR(priv->cru);
810 ret = sdram_init(priv, plat);
814 priv->info.base = CONFIG_SYS_SDRAM_BASE;
815 priv->info.size = rockchip_sdram_size(
816 (phys_addr_t)&priv->grf->os_reg[2]);
822 static int rk322x_dmc_get_info(struct udevice *dev, struct ram_info *info)
824 struct dram_info *priv = dev_get_priv(dev);
831 static struct ram_ops rk322x_dmc_ops = {
832 .get_info = rk322x_dmc_get_info,
835 static const struct udevice_id rk322x_dmc_ids[] = {
836 { .compatible = "rockchip,rk3228-dmc" },
840 U_BOOT_DRIVER(dmc_rk322x) = {
841 .name = "rockchip_rk322x_dmc",
843 .of_match = rk322x_dmc_ids,
844 .ops = &rk322x_dmc_ops,
845 #ifdef CONFIG_TPL_BUILD
846 .ofdata_to_platdata = rk322x_dmc_ofdata_to_platdata,
848 .probe = rk322x_dmc_probe,
849 .priv_auto_alloc_size = sizeof(struct dram_info),
850 #ifdef CONFIG_TPL_BUILD
851 .platdata_auto_alloc_size = sizeof(struct rk322x_sdram_params),