3 * Vikas Manocha, <vikas.manocha@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
14 DECLARE_GLOBAL_DATA_PTR;
16 struct stm32_fmc_regs {
18 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
19 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
20 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
21 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
22 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
23 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
24 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
25 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
29 u32 pcr; /* NAND Flash control register */
30 u32 sr; /* FIFO status and interrupt register */
31 u32 pmem; /* Common memory space timing register */
32 u32 patt; /* Attribute memory space timing registers */
34 u32 eccr; /* ECC result registers */
38 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
40 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
42 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
44 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
48 u32 sdcr1; /* SDRAM Control register 1 */
49 u32 sdcr2; /* SDRAM Control register 2 */
50 u32 sdtr1; /* SDRAM Timing register 1 */
51 u32 sdtr2; /* SDRAM Timing register 2 */
52 u32 sdcmr; /* SDRAM Mode register */
53 u32 sdrtr; /* SDRAM Refresh timing register */
54 u32 sdsr; /* SDRAM Status register */
57 /* Control register SDCR */
58 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
59 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
60 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
61 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
62 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
63 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
64 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
65 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
66 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
68 /* Timings register SDTR */
69 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
70 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
71 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
72 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
73 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
74 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
75 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
77 #define FMC_SDCMR_NRFS_SHIFT 5
79 #define FMC_SDCMR_MODE_NORMAL 0
80 #define FMC_SDCMR_MODE_START_CLOCK 1
81 #define FMC_SDCMR_MODE_PRECHARGE 2
82 #define FMC_SDCMR_MODE_AUTOREFRESH 3
83 #define FMC_SDCMR_MODE_WRITE_MODE 4
84 #define FMC_SDCMR_MODE_SELFREFRESH 5
85 #define FMC_SDCMR_MODE_POWERDOWN 6
87 #define FMC_SDCMR_BANK_1 BIT(4)
88 #define FMC_SDCMR_BANK_2 BIT(3)
90 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
92 #define FMC_SDSR_BUSY BIT(5)
94 #define FMC_BUSY_WAIT(regs) do { \
95 __asm__ __volatile__ ("dsb" : : : "memory"); \
96 while (regs->sdsr & FMC_SDSR_BUSY) \
100 struct stm32_sdram_control {
111 struct stm32_sdram_timing {
120 struct stm32_sdram_params {
121 struct stm32_fmc_regs *base;
123 struct stm32_sdram_control sdram_control;
124 struct stm32_sdram_timing sdram_timing;
128 #define SDRAM_MODE_BL_SHIFT 0
129 #define SDRAM_MODE_CAS_SHIFT 4
130 #define SDRAM_MODE_BL 0
132 int stm32_sdram_init(struct udevice *dev)
134 struct stm32_sdram_params *params = dev_get_platdata(dev);
135 struct stm32_fmc_regs *regs = params->base;
137 writel(params->sdram_control.sdclk << FMC_SDCR_SDCLK_SHIFT
138 | params->sdram_control.cas_latency << FMC_SDCR_CAS_SHIFT
139 | params->sdram_control.no_banks << FMC_SDCR_NB_SHIFT
140 | params->sdram_control.memory_width << FMC_SDCR_MWID_SHIFT
141 | params->sdram_control.no_rows << FMC_SDCR_NR_SHIFT
142 | params->sdram_control.no_columns << FMC_SDCR_NC_SHIFT
143 | params->sdram_control.rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
144 | params->sdram_control.rd_burst << FMC_SDCR_RBURST_SHIFT,
147 writel(params->sdram_timing.trcd << FMC_SDTR_TRCD_SHIFT
148 | params->sdram_timing.trp << FMC_SDTR_TRP_SHIFT
149 | params->sdram_timing.twr << FMC_SDTR_TWR_SHIFT
150 | params->sdram_timing.trc << FMC_SDTR_TRC_SHIFT
151 | params->sdram_timing.tras << FMC_SDTR_TRAS_SHIFT
152 | params->sdram_timing.txsr << FMC_SDTR_TXSR_SHIFT
153 | params->sdram_timing.tmrd << FMC_SDTR_TMRD_SHIFT,
156 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
158 udelay(200); /* 200 us delay, page 10, "Power-Up" */
161 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
166 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
167 | 7 << FMC_SDCMR_NRFS_SHIFT), ®s->sdcmr);
171 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
172 | params->sdram_control.cas_latency << SDRAM_MODE_CAS_SHIFT)
173 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
178 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
183 writel((params->sdram_ref_count) << 1, ®s->sdrtr);
188 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
191 int node = dev_of_offset(dev);
192 const void *blob = gd->fdt_blob;
193 struct stm32_sdram_params *params = dev_get_platdata(dev);
195 params->no_sdram_banks = fdtdec_get_uint(blob, node, "mr-nbanks", 1);
196 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
198 fdt_for_each_subnode(node, blob, node) {
199 ret = fdtdec_get_byte_array(blob, node, "st,sdram-control",
200 (u8 *)¶ms->sdram_control,
201 sizeof(params->sdram_control));
204 ret = fdtdec_get_byte_array(blob, node, "st,sdram-timing",
205 (u8 *)¶ms->sdram_timing,
206 sizeof(params->sdram_timing));
210 params->sdram_ref_count = fdtdec_get_int(blob, node,
211 "st,sdram-refcount", 8196);
217 static int stm32_fmc_probe(struct udevice *dev)
219 struct stm32_sdram_params *params = dev_get_platdata(dev);
223 addr = dev_read_addr(dev);
224 if (addr == FDT_ADDR_T_NONE)
227 params->base = (struct stm32_fmc_regs *)addr;
232 ret = clk_get_by_index(dev, 0, &clk);
236 ret = clk_enable(&clk);
239 dev_err(dev, "failed to enable clock\n");
243 ret = stm32_sdram_init(dev);
250 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
255 static struct ram_ops stm32_fmc_ops = {
256 .get_info = stm32_fmc_get_info,
259 static const struct udevice_id stm32_fmc_ids[] = {
260 { .compatible = "st,stm32-fmc" },
264 U_BOOT_DRIVER(stm32_fmc) = {
267 .of_match = stm32_fmc_ids,
268 .ops = &stm32_fmc_ops,
269 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
270 .probe = stm32_fmc_probe,
271 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),