git.sur5r.net Git - u-boot/blob - drivers/ram/stm32_sdram.c

   1 /*
   2  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <ram.h>
  12 #include <asm/io.h>
  13
  14 #define MEM_MODE_MASK   GENMASK(2, 0)
  15 #define NOT_FOUND       0xff
  16
  17 struct stm32_fmc_regs {
  18         /* 0x0 */
  19         u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  20         u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  21         u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  22         u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  23         u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  24         u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  25         u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  26         u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  27         u32 reserved1[24];
  28
  29         /* 0x80 */
  30         u32 pcr;        /* NAND Flash control register */
  31         u32 sr;         /* FIFO status and interrupt register */
  32         u32 pmem;       /* Common memory space timing register */
  33         u32 patt;       /* Attribute memory space timing registers  */
  34         u32 reserved2[1];
  35         u32 eccr;       /* ECC result registers */
  36         u32 reserved3[27];
  37
  38         /* 0x104 */
  39         u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  40         u32 reserved4[1];
  41         u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  42         u32 reserved5[1];
  43         u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  44         u32 reserved6[1];
  45         u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  46         u32 reserved7[8];
  47
  48         /* 0x140 */
  49         u32 sdcr1;      /* SDRAM Control register 1 */
  50         u32 sdcr2;      /* SDRAM Control register 2 */
  51         u32 sdtr1;      /* SDRAM Timing register 1 */
  52         u32 sdtr2;      /* SDRAM Timing register 2 */
  53         u32 sdcmr;      /* SDRAM Mode register */
  54         u32 sdrtr;      /* SDRAM Refresh timing register */
  55         u32 sdsr;       /* SDRAM Status register */
  56 };
  57
  58 /*
  59  * NOR/PSRAM Control register BCR1
  60  * FMC controller Enable, only availabe for H7
  61  */
  62 #define FMC_BCR1_FMCEN          BIT(31)
  63
  64 /* Control register SDCR */
  65 #define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  66 #define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  67 #define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  68 #define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  69 #define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  70 #define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  71 #define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  72 #define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  73 #define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  74
  75 /* Timings register SDTR */
  76 #define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  77 #define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  78 #define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  79 #define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  80 #define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  81 #define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  82 #define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  83
  84 #define FMC_SDCMR_NRFS_SHIFT    5
  85
  86 #define FMC_SDCMR_MODE_NORMAL           0
  87 #define FMC_SDCMR_MODE_START_CLOCK      1
  88 #define FMC_SDCMR_MODE_PRECHARGE        2
  89 #define FMC_SDCMR_MODE_AUTOREFRESH      3
  90 #define FMC_SDCMR_MODE_WRITE_MODE       4
  91 #define FMC_SDCMR_MODE_SELFREFRESH      5
  92 #define FMC_SDCMR_MODE_POWERDOWN        6
  93
  94 #define FMC_SDCMR_BANK_1                BIT(4)
  95 #define FMC_SDCMR_BANK_2                BIT(3)
  96
  97 #define FMC_SDCMR_MODE_REGISTER_SHIFT   9
  98
  99 #define FMC_SDSR_BUSY                   BIT(5)
 100
 101 #define FMC_BUSY_WAIT(regs)     do { \
 102                 __asm__ __volatile__ ("dsb" : : : "memory"); \
 103                 while (regs->sdsr & FMC_SDSR_BUSY) \
 104                         ; \
 105         } while (0)
 106
 107 struct stm32_sdram_control {
 108         u8 no_columns;
 109         u8 no_rows;
 110         u8 memory_width;
 111         u8 no_banks;
 112         u8 cas_latency;
 113         u8 sdclk;
 114         u8 rd_burst;
 115         u8 rd_pipe_delay;
 116 };
 117
 118 struct stm32_sdram_timing {
 119         u8 tmrd;
 120         u8 txsr;
 121         u8 tras;
 122         u8 trc;
 123         u8 trp;
 124         u8 twr;
 125         u8 trcd;
 126 };
 127 enum stm32_fmc_bank {
 128         SDRAM_BANK1,
 129         SDRAM_BANK2,
 130         MAX_SDRAM_BANK,
 131 };
 132
 133 enum stm32_fmc_family {
 134         STM32F7_FMC,
 135         STM32H7_FMC,
 136 };
 137
 138 struct bank_params {
 139         struct stm32_sdram_control *sdram_control;
 140         struct stm32_sdram_timing *sdram_timing;
 141         u32 sdram_ref_count;
 142         enum stm32_fmc_bank target_bank;
 143 };
 144
 145 struct stm32_sdram_params {
 146         struct stm32_fmc_regs *base;
 147         u8 no_sdram_banks;
 148         struct bank_params bank_params[MAX_SDRAM_BANK];
 149         enum stm32_fmc_family family;
 150 };
 151
 152 #define SDRAM_MODE_BL_SHIFT     0
 153 #define SDRAM_MODE_CAS_SHIFT    4
 154 #define SDRAM_MODE_BL           0
 155
 156 int stm32_sdram_init(struct udevice *dev)
 157 {
 158         struct stm32_sdram_params *params = dev_get_platdata(dev);
 159         struct stm32_sdram_control *control;
 160         struct stm32_sdram_timing *timing;
 161         struct stm32_fmc_regs *regs = params->base;
 162         enum stm32_fmc_bank target_bank;
 163         u32 ctb; /* SDCMR register: Command Target Bank */
 164         u32 ref_count;
 165         u8 i;
 166
 167         /* disable the FMC controller */
 168         if (params->family == STM32H7_FMC)
 169                 clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 170
 171         for (i = 0; i < params->no_sdram_banks; i++) {
 172                 control = params->bank_params[i].sdram_control;
 173                 timing = params->bank_params[i].sdram_timing;
 174                 target_bank = params->bank_params[i].target_bank;
 175                 ref_count = params->bank_params[i].sdram_ref_count;
 176
 177                 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 178                         | control->cas_latency << FMC_SDCR_CAS_SHIFT
 179                         | control->no_banks << FMC_SDCR_NB_SHIFT
 180                         | control->memory_width << FMC_SDCR_MWID_SHIFT
 181                         | control->no_rows << FMC_SDCR_NR_SHIFT
 182                         | control->no_columns << FMC_SDCR_NC_SHIFT
 183                         | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 184                         | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 185                         &regs->sdcr1);
 186
 187                 if (target_bank == SDRAM_BANK2)
 188                         writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
 189                                 | control->no_banks << FMC_SDCR_NB_SHIFT
 190                                 | control->memory_width << FMC_SDCR_MWID_SHIFT
 191                                 | control->no_rows << FMC_SDCR_NR_SHIFT
 192                                 | control->no_columns << FMC_SDCR_NC_SHIFT,
 193                                 &regs->sdcr2);
 194
 195                 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 196                         | timing->trp << FMC_SDTR_TRP_SHIFT
 197                         | timing->twr << FMC_SDTR_TWR_SHIFT
 198                         | timing->trc << FMC_SDTR_TRC_SHIFT
 199                         | timing->tras << FMC_SDTR_TRAS_SHIFT
 200                         | timing->txsr << FMC_SDTR_TXSR_SHIFT
 201                         | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 202                         &regs->sdtr1);
 203
 204                 if (target_bank == SDRAM_BANK2)
 205                         writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 206                                 | timing->trp << FMC_SDTR_TRP_SHIFT
 207                                 | timing->twr << FMC_SDTR_TWR_SHIFT
 208                                 | timing->trc << FMC_SDTR_TRC_SHIFT
 209                                 | timing->tras << FMC_SDTR_TRAS_SHIFT
 210                                 | timing->txsr << FMC_SDTR_TXSR_SHIFT
 211                                 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 212                                 &regs->sdtr2);
 213
 214                 if (target_bank == SDRAM_BANK1)
 215                         ctb = FMC_SDCMR_BANK_1;
 216                 else
 217                         ctb = FMC_SDCMR_BANK_2;
 218
 219                 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
 220                 udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 221                 FMC_BUSY_WAIT(regs);
 222
 223                 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
 224                 udelay(100);
 225                 FMC_BUSY_WAIT(regs);
 226
 227                 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
 228                        &regs->sdcmr);
 229                 udelay(100);
 230                 FMC_BUSY_WAIT(regs);
 231
 232                 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 233                        | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 234                        << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 235                        &regs->sdcmr);
 236                 udelay(100);
 237                 FMC_BUSY_WAIT(regs);
 238
 239                 writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
 240                 FMC_BUSY_WAIT(regs);
 241
 242                 /* Refresh timer */
 243                 writel(ref_count << 1, &regs->sdrtr);
 244         }
 245
 246         /* enable the FMC controller */
 247         if (params->family == STM32H7_FMC)
 248                 setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
 249
 250         return 0;
 251 }
 252
 253 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 254 {
 255         struct stm32_sdram_params *params = dev_get_platdata(dev);
 256         struct bank_params *bank_params;
 257         struct ofnode_phandle_args args;
 258         u32 *syscfg_base;
 259         u32 mem_remap;
 260         ofnode bank_node;
 261         char *bank_name;
 262         u8 bank = 0;
 263         int ret;
 264
 265         mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
 266         if (mem_remap != NOT_FOUND) {
 267                 ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
 268                                                  &args);
 269                 if (ret) {
 270                         debug("%s: can't find syscon device (%d)\n", __func__,
 271                               ret);
 272                         return ret;
 273                 }
 274
 275                 syscfg_base = (u32 *)ofnode_get_addr(args.node);
 276
 277                 /* set memory mapping selection */
 278                 clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
 279         } else {
 280                 debug("%s: cannot find st,mem_remap property\n", __func__);
 281         }
 282
 283         dev_for_each_subnode(bank_node, dev) {
 284                 /* extract the bank index from DT */
 285                 bank_name = (char *)ofnode_get_name(bank_node);
 286                 strsep(&bank_name, "@");
 287                 if (!bank_name) {
 288                         pr_err("missing sdram bank index");
 289                         return -EINVAL;
 290                 }
 291
 292                 bank_params = &params->bank_params[bank];
 293                 strict_strtoul(bank_name, 10,
 294                                (long unsigned int *)&bank_params->target_bank);
 295
 296                 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
 297                         pr_err("Found bank %d , but only bank 0 and 1 are supported",
 298                               bank_params->target_bank);
 299                         return -EINVAL;
 300                 }
 301
 302                 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
 303
 304                 params->bank_params[bank].sdram_control =
 305                         (struct stm32_sdram_control *)
 306                          ofnode_read_u8_array_ptr(bank_node,
 307                                                   "st,sdram-control",
 308                                                   sizeof(struct stm32_sdram_control));
 309
 310                 if (!params->bank_params[bank].sdram_control) {
 311                         pr_err("st,sdram-control not found for %s",
 312                               ofnode_get_name(bank_node));
 313                         return -EINVAL;
 314                 }
 315
 316
 317                 params->bank_params[bank].sdram_timing =
 318                         (struct stm32_sdram_timing *)
 319                          ofnode_read_u8_array_ptr(bank_node,
 320                                                   "st,sdram-timing",
 321                                                   sizeof(struct stm32_sdram_timing));
 322
 323                 if (!params->bank_params[bank].sdram_timing) {
 324                         pr_err("st,sdram-timing not found for %s",
 325                               ofnode_get_name(bank_node));
 326                         return -EINVAL;
 327                 }
 328
 329
 330                 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 331                                                 "st,sdram-refcount", 8196);
 332                 bank++;
 333         }
 334
 335         params->no_sdram_banks = bank;
 336         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 337
 338         return 0;
 339 }
 340
 341 static int stm32_fmc_probe(struct udevice *dev)
 342 {
 343         struct stm32_sdram_params *params = dev_get_platdata(dev);
 344         int ret;
 345         fdt_addr_t addr;
 346
 347         addr = dev_read_addr(dev);
 348         if (addr == FDT_ADDR_T_NONE)
 349                 return -EINVAL;
 350
 351         params->base = (struct stm32_fmc_regs *)addr;
 352         params->family = dev_get_driver_data(dev);
 353
 354 #ifdef CONFIG_CLK
 355         struct clk clk;
 356
 357         ret = clk_get_by_index(dev, 0, &clk);
 358         if (ret < 0)
 359                 return ret;
 360
 361         ret = clk_enable(&clk);
 362
 363         if (ret) {
 364                 dev_err(dev, "failed to enable clock\n");
 365                 return ret;
 366         }
 367 #endif
 368         ret = stm32_sdram_init(dev);
 369         if (ret)
 370                 return ret;
 371
 372         return 0;
 373 }
 374
 375 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 376 {
 377         return 0;
 378 }
 379
 380 static struct ram_ops stm32_fmc_ops = {
 381         .get_info = stm32_fmc_get_info,
 382 };
 383
 384 static const struct udevice_id stm32_fmc_ids[] = {
 385         { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
 386         { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
 387         { }
 388 };
 389
 390 U_BOOT_DRIVER(stm32_fmc) = {
 391         .name = "stm32_fmc",
 392         .id = UCLASS_RAM,
 393         .of_match = stm32_fmc_ids,
 394         .ops = &stm32_fmc_ops,
 395         .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
 396         .probe = stm32_fmc_probe,
 397         .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
 398 };