git.sur5r.net Git - u-boot/blob - drivers/ram/stm32_sdram.c

   1 /*
   2  * (C) Copyright 2017
   3  * Vikas Manocha, <vikas.manocha@st.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <ram.h>
  12 #include <asm/io.h>
  13
  14 DECLARE_GLOBAL_DATA_PTR;
  15
  16 struct stm32_fmc_regs {
  17         /* 0x0 */
  18         u32 bcr1;       /* NOR/PSRAM Chip select control register 1 */
  19         u32 btr1;       /* SRAM/NOR-Flash Chip select timing register 1 */
  20         u32 bcr2;       /* NOR/PSRAM Chip select Control register 2 */
  21         u32 btr2;       /* SRAM/NOR-Flash Chip select timing register 2 */
  22         u32 bcr3;       /* NOR/PSRAMChip select Control register 3 */
  23         u32 btr3;       /* SRAM/NOR-Flash Chip select timing register 3 */
  24         u32 bcr4;       /* NOR/PSRAM Chip select Control register 4 */
  25         u32 btr4;       /* SRAM/NOR-Flash Chip select timing register 4 */
  26         u32 reserved1[24];
  27
  28         /* 0x80 */
  29         u32 pcr;        /* NAND Flash control register */
  30         u32 sr;         /* FIFO status and interrupt register */
  31         u32 pmem;       /* Common memory space timing register */
  32         u32 patt;       /* Attribute memory space timing registers  */
  33         u32 reserved2[1];
  34         u32 eccr;       /* ECC result registers */
  35         u32 reserved3[27];
  36
  37         /* 0x104 */
  38         u32 bwtr1;      /* SRAM/NOR-Flash write timing register 1 */
  39         u32 reserved4[1];
  40         u32 bwtr2;      /* SRAM/NOR-Flash write timing register 2 */
  41         u32 reserved5[1];
  42         u32 bwtr3;      /* SRAM/NOR-Flash write timing register 3 */
  43         u32 reserved6[1];
  44         u32 bwtr4;      /* SRAM/NOR-Flash write timing register 4 */
  45         u32 reserved7[8];
  46
  47         /* 0x140 */
  48         u32 sdcr1;      /* SDRAM Control register 1 */
  49         u32 sdcr2;      /* SDRAM Control register 2 */
  50         u32 sdtr1;      /* SDRAM Timing register 1 */
  51         u32 sdtr2;      /* SDRAM Timing register 2 */
  52         u32 sdcmr;      /* SDRAM Mode register */
  53         u32 sdrtr;      /* SDRAM Refresh timing register */
  54         u32 sdsr;       /* SDRAM Status register */
  55 };
  56
  57 /* Control register SDCR */
  58 #define FMC_SDCR_RPIPE_SHIFT    13      /* RPIPE bit shift */
  59 #define FMC_SDCR_RBURST_SHIFT   12      /* RBURST bit shift */
  60 #define FMC_SDCR_SDCLK_SHIFT    10      /* SDRAM clock divisor shift */
  61 #define FMC_SDCR_WP_SHIFT       9       /* Write protection shift */
  62 #define FMC_SDCR_CAS_SHIFT      7       /* CAS latency shift */
  63 #define FMC_SDCR_NB_SHIFT       6       /* Number of banks shift */
  64 #define FMC_SDCR_MWID_SHIFT     4       /* Memory width shift */
  65 #define FMC_SDCR_NR_SHIFT       2       /* Number of row address bits shift */
  66 #define FMC_SDCR_NC_SHIFT       0       /* Number of col address bits shift */
  67
  68 /* Timings register SDTR */
  69 #define FMC_SDTR_TMRD_SHIFT     0       /* Load mode register to active */
  70 #define FMC_SDTR_TXSR_SHIFT     4       /* Exit self-refresh time */
  71 #define FMC_SDTR_TRAS_SHIFT     8       /* Self-refresh time */
  72 #define FMC_SDTR_TRC_SHIFT      12      /* Row cycle delay */
  73 #define FMC_SDTR_TWR_SHIFT      16      /* Recovery delay */
  74 #define FMC_SDTR_TRP_SHIFT      20      /* Row precharge delay */
  75 #define FMC_SDTR_TRCD_SHIFT     24      /* Row-to-column delay */
  76
  77 #define FMC_SDCMR_NRFS_SHIFT    5
  78
  79 #define FMC_SDCMR_MODE_NORMAL           0
  80 #define FMC_SDCMR_MODE_START_CLOCK      1
  81 #define FMC_SDCMR_MODE_PRECHARGE        2
  82 #define FMC_SDCMR_MODE_AUTOREFRESH      3
  83 #define FMC_SDCMR_MODE_WRITE_MODE       4
  84 #define FMC_SDCMR_MODE_SELFREFRESH      5
  85 #define FMC_SDCMR_MODE_POWERDOWN        6
  86
  87 #define FMC_SDCMR_BANK_1                BIT(4)
  88 #define FMC_SDCMR_BANK_2                BIT(3)
  89
  90 #define FMC_SDCMR_MODE_REGISTER_SHIFT   9
  91
  92 #define FMC_SDSR_BUSY                   BIT(5)
  93
  94 #define FMC_BUSY_WAIT(regs)     do { \
  95                 __asm__ __volatile__ ("dsb" : : : "memory"); \
  96                 while (regs->sdsr & FMC_SDSR_BUSY) \
  97                         ; \
  98         } while (0)
  99
 100 struct stm32_sdram_control {
 101         u8 no_columns;
 102         u8 no_rows;
 103         u8 memory_width;
 104         u8 no_banks;
 105         u8 cas_latency;
 106         u8 sdclk;
 107         u8 rd_burst;
 108         u8 rd_pipe_delay;
 109 };
 110
 111 struct stm32_sdram_timing {
 112         u8 tmrd;
 113         u8 txsr;
 114         u8 tras;
 115         u8 trc;
 116         u8 trp;
 117         u8 twr;
 118         u8 trcd;
 119 };
 120 struct stm32_sdram_params {
 121         struct stm32_fmc_regs *base;
 122         u8 no_sdram_banks;
 123         struct stm32_sdram_control *sdram_control;
 124         struct stm32_sdram_timing *sdram_timing;
 125         u32 sdram_ref_count;
 126 };
 127
 128 #define SDRAM_MODE_BL_SHIFT     0
 129 #define SDRAM_MODE_CAS_SHIFT    4
 130 #define SDRAM_MODE_BL           0
 131
 132 int stm32_sdram_init(struct udevice *dev)
 133 {
 134         struct stm32_sdram_params *params = dev_get_platdata(dev);
 135         struct stm32_fmc_regs *regs = params->base;
 136         struct stm32_sdram_control *control = params->sdram_control;
 137         struct stm32_sdram_timing *timing = params->sdram_timing;
 138
 139         writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
 140                 | control->cas_latency << FMC_SDCR_CAS_SHIFT
 141                 | control->no_banks << FMC_SDCR_NB_SHIFT
 142                 | control->memory_width << FMC_SDCR_MWID_SHIFT
 143                 | control->no_rows << FMC_SDCR_NR_SHIFT
 144                 | control->no_columns << FMC_SDCR_NC_SHIFT
 145                 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
 146                 | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
 147                 &regs->sdcr1);
 148
 149         writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
 150                 | timing->trp << FMC_SDTR_TRP_SHIFT
 151                 | timing->twr << FMC_SDTR_TWR_SHIFT
 152                 | timing->trc << FMC_SDTR_TRC_SHIFT
 153                 | timing->tras << FMC_SDTR_TRAS_SHIFT
 154                 | timing->txsr << FMC_SDTR_TXSR_SHIFT
 155                 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
 156                 &regs->sdtr1);
 157
 158         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
 159                &regs->sdcmr);
 160         udelay(200);    /* 200 us delay, page 10, "Power-Up" */
 161         FMC_BUSY_WAIT(regs);
 162
 163         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
 164                &regs->sdcmr);
 165         udelay(100);
 166         FMC_BUSY_WAIT(regs);
 167
 168         writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
 169                 | 7 << FMC_SDCMR_NRFS_SHIFT), &regs->sdcmr);
 170         udelay(100);
 171         FMC_BUSY_WAIT(regs);
 172
 173         writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
 174                | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
 175                << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
 176                &regs->sdcmr);
 177         udelay(100);
 178         FMC_BUSY_WAIT(regs);
 179
 180         writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
 181                &regs->sdcmr);
 182         FMC_BUSY_WAIT(regs);
 183
 184         /* Refresh timer */
 185         writel((params->sdram_ref_count) << 1, &regs->sdrtr);
 186
 187         return 0;
 188 }
 189
 190 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
 191 {
 192         ofnode bank_node;
 193         struct stm32_sdram_params *params = dev_get_platdata(dev);
 194
 195         params->no_sdram_banks = dev_read_u32_default(dev, "mr-nbanks", 1);
 196         debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
 197
 198         dev_for_each_subnode(bank_node, dev) {
 199                 params->sdram_control = (struct stm32_sdram_control *)
 200                                         ofnode_read_u8_array_ptr(bank_node,
 201                                                 "st,sdram-control",
 202                                                 sizeof(struct stm32_sdram_control));
 203
 204                 if (!params->sdram_control) {
 205                         error("st,sdram-control not found for device: %s",
 206                               dev->name);
 207                         return -EINVAL;
 208                 }
 209
 210                 params->sdram_timing = (struct stm32_sdram_timing *)
 211                                         ofnode_read_u8_array_ptr(bank_node,
 212                                                 "st,sdram-timing",
 213                                                 sizeof(struct stm32_sdram_timing));
 214
 215                 if (!params->sdram_timing) {
 216                         error("st,sdram-timing not found for device: %s",
 217                               dev->name);
 218                         return -EINVAL;
 219                 }
 220
 221                 params->sdram_ref_count = ofnode_read_u32_default(bank_node,
 222                                                 "st,sdram-refcount", 8196);
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int stm32_fmc_probe(struct udevice *dev)
 229 {
 230         struct stm32_sdram_params *params = dev_get_platdata(dev);
 231         int ret;
 232         fdt_addr_t addr;
 233
 234         addr = dev_read_addr(dev);
 235         if (addr == FDT_ADDR_T_NONE)
 236                 return -EINVAL;
 237
 238         params->base = (struct stm32_fmc_regs *)addr;
 239
 240 #ifdef CONFIG_CLK
 241         struct clk clk;
 242
 243         ret = clk_get_by_index(dev, 0, &clk);
 244         if (ret < 0)
 245                 return ret;
 246
 247         ret = clk_enable(&clk);
 248
 249         if (ret) {
 250                 dev_err(dev, "failed to enable clock\n");
 251                 return ret;
 252         }
 253 #endif
 254         ret = stm32_sdram_init(dev);
 255         if (ret)
 256                 return ret;
 257
 258         return 0;
 259 }
 260
 261 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
 262 {
 263         return 0;
 264 }
 265
 266 static struct ram_ops stm32_fmc_ops = {
 267         .get_info = stm32_fmc_get_info,
 268 };
 269
 270 static const struct udevice_id stm32_fmc_ids[] = {
 271         { .compatible = "st,stm32-fmc" },
 272         { }
 273 };
 274
 275 U_BOOT_DRIVER(stm32_fmc) = {
 276         .name = "stm32_fmc",
 277         .id = UCLASS_RAM,
 278         .of_match = stm32_fmc_ids,
 279         .ops = &stm32_fmc_ops,
 280         .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
 281         .probe = stm32_fmc_probe,
 282         .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),
 283 };