2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from rtl8139.c of etherboot
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
24 /*********************************************************************/
25 /* Revision History */
26 /*********************************************************************/
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
47 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
48 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
56 interrupts. This confused the RTL8139 thoroughly. It destroyed the
57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
60 18 Jan 2000 mdc@thinguin.org (Marty Connor)
61 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
64 save buffer space. This should decrease driver size and avoid
65 corruption because of exceeding 32K during runtime.
67 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
68 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
81 static unsigned long mips_io_port_base = 0;
84 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
85 defined(CONFIG_RTL8139)
87 #define TICKS_PER_SEC CFG_HZ
88 #define TICKS_PER_MS (TICKS_PER_SEC/1000)
90 #define RTL_TIMEOUT (1*TICKS_PER_SEC)
92 #define ETH_FRAME_LEN 1514
96 /* PCI Tuning Parameters
97 Threshold is bytes transferred to chip before transmission starts. */
98 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
99 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
100 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
101 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */
102 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
103 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
104 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
105 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
110 #define currticks() get_timer(0)
111 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
112 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
114 /* Symbolic offsets to registers. */
115 enum RTL8139_registers {
116 MAC0=0, /* Ethernet hardware address. */
117 MAR0=8, /* Multicast filter. */
118 TxStatus0=0x10, /* Transmit status (four 32bit registers). */
119 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
120 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
121 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
122 IntrMask=0x3C, IntrStatus=0x3E,
123 TxConfig=0x40, RxConfig=0x44,
124 Timer=0x48, /* general-purpose counter. */
125 RxMissed=0x4C, /* 24 bits valid, write clears. */
126 Cfg9346=0x50, Config0=0x51, Config1=0x52,
127 TimerIntrReg=0x54, /* intr if gp counter reaches this value */
131 RevisionID=0x5E, /* revision of the RTL8139 chip */
133 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
135 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
137 RxCnt=0x72, /* packet received counter */
138 CSCR=0x74, /* chip status and configuration register */
139 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
140 /* from 0x84 onwards are a number of power management/wakeup frame
141 * definitions we will probably never need to know about. */
145 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
147 /* Interrupt register bits, using my own meaningful names. */
148 enum IntrStatusBits {
149 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
150 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
151 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
154 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
155 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
156 TxCarrierLost=0x80000000,
159 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
160 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
161 RxBadAlign=0x0002, RxStatusOK=0x0001,
164 enum MediaStatusBits {
165 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
166 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
170 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
171 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
175 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
176 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
177 CSCR_LinkDownCmd=0x0f3c0,
180 /* Bits in RxConfig. */
183 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
184 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
188 static unsigned int cur_rx,cur_tx;
190 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */
191 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
192 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
194 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
195 static int read_eeprom(int location, int addr_len);
196 static void rtl_reset(struct eth_device *dev);
197 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
198 static int rtl_poll(struct eth_device *dev);
199 static void rtl_disable(struct eth_device *dev);
201 static struct pci_device_id supported[] = {
202 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
206 int rtl8139_initialize(bd_t *bis)
210 struct eth_device *dev;
216 if ((devno = pci_find_devices(supported, idx++)) < 0)
219 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
222 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
224 dev = (struct eth_device *)malloc(sizeof *dev);
226 sprintf (dev->name, "RTL8139#%d", card_number);
228 dev->priv = (void *) devno;
229 dev->iobase = (int)bus_to_phys(iobase);
230 dev->init = rtl8139_probe;
231 dev->halt = rtl_disable;
232 dev->send = rtl_transmit;
233 dev->recv = rtl_poll;
239 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
247 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
250 int speed10, fullduplex;
252 unsigned short *ap = (unsigned short *)dev->enetaddr;
254 ioaddr = dev->iobase;
256 /* Bring the chip out of low-power mode. */
257 outb(0x00, ioaddr + Config1);
259 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
260 for (i = 0; i < 3; i++)
261 *ap++ = read_eeprom(i + 7, addr_len);
263 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
264 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
268 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
269 printf("Cable not connected or other link failure\n");
276 /* Serial EEPROM section. */
278 /* EEPROM_Ctrl bits. */
279 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
280 #define EE_CS 0x08 /* EEPROM chip select. */
281 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
282 #define EE_WRITE_0 0x00
283 #define EE_WRITE_1 0x02
284 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
285 #define EE_ENB (0x80 | EE_CS)
288 Delay between EEPROM clock transitions.
289 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
292 #define eeprom_delay() inl(ee_addr)
294 /* The EEPROM commands include the alway-set leading bit. */
295 #define EE_WRITE_CMD (5)
296 #define EE_READ_CMD (6)
297 #define EE_ERASE_CMD (7)
299 static int read_eeprom(int location, int addr_len)
302 unsigned int retval = 0;
303 long ee_addr = ioaddr + Cfg9346;
304 int read_cmd = location | (EE_READ_CMD << addr_len);
306 outb(EE_ENB & ~EE_CS, ee_addr);
307 outb(EE_ENB, ee_addr);
310 /* Shift the read command bits out. */
311 for (i = 4 + addr_len; i >= 0; i--) {
312 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
313 outb(EE_ENB | dataval, ee_addr);
315 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
318 outb(EE_ENB, ee_addr);
321 for (i = 16; i > 0; i--) {
322 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
324 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
325 outb(EE_ENB, ee_addr);
329 /* Terminate the EEPROM access. */
330 outb(~EE_CS, ee_addr);
335 static const unsigned int rtl8139_rx_config =
336 (RX_BUF_LEN_IDX << 11) |
337 (RX_FIFO_THRESH << 13) |
340 static void set_rx_mode(struct eth_device *dev) {
341 unsigned int mc_filter[2];
344 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
345 mc_filter[1] = mc_filter[0] = 0xffffffff;
347 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
349 outl(mc_filter[0], ioaddr + MAR0 + 0);
350 outl(mc_filter[1], ioaddr + MAR0 + 4);
353 static void rtl_reset(struct eth_device *dev)
357 outb(CmdReset, ioaddr + ChipCmd);
362 /* Give the chip 10ms to finish the reset. */
363 for (i=0; i<100; ++i){
364 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
365 udelay (100); /* wait 100us */
369 for (i = 0; i < ETH_ALEN; i++)
370 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
372 /* Must enable Tx/Rx before setting transfer thresholds! */
373 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
374 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
375 ioaddr + RxConfig); /* accept no frames yet! */
376 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
378 /* The Linux driver changes Config1 here to use a different LED pattern
379 * for half duplex or full/autodetect duplex (for full/autodetect, the
380 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
381 * TX/RX, Link100, Link10). This is messy, because it doesn't match
382 * the inscription on the mounting bracket. It should not be changed
383 * from the configuration EEPROM default, because the card manufacturer
384 * should have set that to match the card. */
387 printf("rx ring address is %X\n",(unsigned long)rx_ring);
389 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
391 /* If we add multicast support, the MAR0 register would have to be
392 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
393 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
395 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
397 outl(rtl8139_rx_config, ioaddr + RxConfig);
399 /* Start the chip's Tx and Rx process. */
400 outl(0, ioaddr + RxMissed);
405 /* Disable all known interrupts by setting the interrupt mask. */
406 outw(0, ioaddr + IntrMask);
409 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
411 unsigned int status, to;
412 unsigned long txstatus;
413 unsigned int len = length;
415 ioaddr = dev->iobase;
417 memcpy((char *)tx_buffer, (char *)packet, (int)length);
420 printf("sending %d bytes\n", len);
423 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
424 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
425 while (len < ETH_ZLEN) {
426 tx_buffer[len++] = '\0';
429 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
430 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
431 ioaddr + TxStatus0 + cur_tx*4);
433 to = currticks() + RTL_TIMEOUT;
436 status = inw(ioaddr + IntrStatus);
437 /* Only acknlowledge interrupt sources we can properly handle
438 * here - the RxOverflow/RxFIFOOver MUST be handled in the
439 * rtl_poll() function. */
440 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
441 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
442 } while (currticks() < to);
444 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
447 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
449 printf("tx done (%d ticks), status %hX txstatus %X\n",
450 to-currticks(), status, txstatus);
455 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
456 currticks()-to, status, txstatus);
464 static int rtl_poll(struct eth_device *dev)
467 unsigned int ring_offs;
468 unsigned int rx_size, rx_status;
471 ioaddr = dev->iobase;
473 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
477 status = inw(ioaddr + IntrStatus);
478 /* See below for the rest of the interrupt acknowledges. */
479 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
482 printf("rtl_poll: int %hX ", status);
485 ring_offs = cur_rx % RX_BUF_LEN;
486 rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs));
487 rx_size = rx_status >> 16;
490 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
491 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
492 printf("rx error %hX\n", rx_status);
493 rtl_reset(dev); /* this clears all interrupts still pending */
497 /* Received a good packet */
498 length = rx_size - 4; /* no one cares about the FCS */
499 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
500 int semi_count = RX_BUF_LEN - ring_offs - 4;
501 unsigned char rxdata[RX_BUF_LEN];
503 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
504 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
506 NetReceive(rxdata, length);
508 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
511 NetReceive(rx_ring + ring_offs + 4, length);
513 printf("rx packet %d bytes", rx_size-4);
517 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
518 outw(cur_rx - 16, ioaddr + RxBufPtr);
519 /* See RTL8139 Programming Guide V0.1 for the official handling of
520 * Rx overflow situations. The document itself contains basically no
521 * usable information, except for a few exception handling rules. */
522 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
526 static void rtl_disable(struct eth_device *dev)
531 outb(CmdReset, ioaddr + ChipCmd);
533 /* Give the chip 10ms to finish the reset. */
534 for (i=0; i<100; ++i){
535 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
536 udelay (100); /* wait 100us */
539 #endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */