2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
16 #define US1_TDRE (1 << 7)
17 #define US1_RDRF (1 << 5)
18 #define US1_OR (1 << 3)
19 #define UC2_TE (1 << 3)
20 #define UC2_RE (1 << 2)
21 #define CFIFO_TXFLUSH (1 << 7)
22 #define CFIFO_RXFLUSH (1 << 6)
23 #define SFIFO_RXOF (1 << 2)
24 #define SFIFO_RXUF (1 << 0)
26 #define STAT_LBKDIF (1 << 31)
27 #define STAT_RXEDGIF (1 << 30)
28 #define STAT_TDRE (1 << 23)
29 #define STAT_RDRF (1 << 21)
30 #define STAT_IDLE (1 << 20)
31 #define STAT_OR (1 << 19)
32 #define STAT_NF (1 << 18)
33 #define STAT_FE (1 << 17)
34 #define STAT_PF (1 << 16)
35 #define STAT_MA1F (1 << 15)
36 #define STAT_MA2F (1 << 14)
37 #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
38 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
40 #define CTRL_TE (1 << 19)
41 #define CTRL_RE (1 << 18)
43 #define FIFO_TXFE 0x80
44 #define FIFO_RXFE 0x40
46 #define WATER_TXWATER_OFF 1
47 #define WATER_RXWATER_OFF 16
49 DECLARE_GLOBAL_DATA_PTR;
51 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
53 struct lpuart_serial_platdata {
54 struct lpuart_fsl *reg;
57 #ifndef CONFIG_LPUART_32B_REG
58 static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
60 u32 clk = mxc_get_clock(MXC_UART_CLK);
63 sbr = (u16)(clk / (16 * baudrate));
65 /* place adjustment later - n/32 BRFA */
66 __raw_writeb(sbr >> 8, &base->ubdh);
67 __raw_writeb(sbr & 0xff, &base->ubdl);
70 static int _lpuart_serial_getc(struct lpuart_fsl *base)
72 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
77 return __raw_readb(&base->ud);
80 static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
83 _lpuart_serial_putc(base, '\r');
85 while (!(__raw_readb(&base->us1) & US1_TDRE))
88 __raw_writeb(c, &base->ud);
91 /* Test whether a character is in the RX buffer */
92 static int _lpuart_serial_tstc(struct lpuart_fsl *base)
94 if (__raw_readb(&base->urcfifo) == 0)
101 * Initialise the serial port with the given baudrate. The settings
102 * are always 8 data bits, no parity, 1 stop bit, no start bits.
104 static int _lpuart_serial_init(struct lpuart_fsl *base)
108 ctrl = __raw_readb(&base->uc2);
111 __raw_writeb(ctrl, &base->uc2);
113 __raw_writeb(0, &base->umodem);
114 __raw_writeb(0, &base->uc1);
116 /* Disable FIFO and flush buffer */
117 __raw_writeb(0x0, &base->upfifo);
118 __raw_writeb(0x0, &base->utwfifo);
119 __raw_writeb(0x1, &base->urwfifo);
120 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
122 /* provide data bits, parity, stop bit, etc */
123 _lpuart_serial_setbrg(base, gd->baudrate);
125 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
130 #ifndef CONFIG_DM_SERIAL
131 static void lpuart_serial_setbrg(void)
133 _lpuart_serial_setbrg(base, gd->baudrate);
136 static int lpuart_serial_getc(void)
138 return _lpuart_serial_getc(base);
141 static void lpuart_serial_putc(const char c)
143 _lpuart_serial_putc(base, c);
146 static int lpuart_serial_tstc(void)
148 return _lpuart_serial_tstc(base);
151 static int lpuart_serial_init(void)
153 return _lpuart_serial_init(base);
156 static struct serial_device lpuart_serial_drv = {
157 .name = "lpuart_serial",
158 .start = lpuart_serial_init,
160 .setbrg = lpuart_serial_setbrg,
161 .putc = lpuart_serial_putc,
162 .puts = default_serial_puts,
163 .getc = lpuart_serial_getc,
164 .tstc = lpuart_serial_tstc,
166 #else /* CONFIG_DM_SERIAL */
167 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
169 struct lpuart_serial_platdata *plat = dev->platdata;
170 struct lpuart_fsl *reg = plat->reg;
172 _lpuart_serial_setbrg(reg, baudrate);
177 static int lpuart_serial_getc(struct udevice *dev)
179 struct lpuart_serial_platdata *plat = dev->platdata;
180 struct lpuart_fsl *reg = plat->reg;
182 return _lpuart_serial_getc(reg);
185 static int lpuart_serial_putc(struct udevice *dev, const char c)
187 struct lpuart_serial_platdata *plat = dev->platdata;
188 struct lpuart_fsl *reg = plat->reg;
190 _lpuart_serial_putc(reg, c);
195 static int lpuart_serial_pending(struct udevice *dev, bool input)
197 struct lpuart_serial_platdata *plat = dev->platdata;
198 struct lpuart_fsl *reg = plat->reg;
201 return _lpuart_serial_tstc(reg);
203 return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
206 static int lpuart_serial_probe(struct udevice *dev)
208 struct lpuart_serial_platdata *plat = dev->platdata;
209 struct lpuart_fsl *reg = plat->reg;
211 return _lpuart_serial_init(reg);
213 #endif /* CONFIG_DM_SERIAL */
215 static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
217 u32 clk = CONFIG_SYS_CLK_FREQ;
220 sbr = (clk / (16 * baudrate));
222 /* place adjustment later - n/32 BRFA */
223 out_be32(&base->baud, sbr);
226 static int _lpuart32_serial_getc(struct lpuart_fsl *base)
230 while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
231 out_be32(&base->stat, STAT_FLAGS);
235 return in_be32(&base->data) & 0x3ff;
238 static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
241 _lpuart32_serial_putc(base, '\r');
243 while (!(in_be32(&base->stat) & STAT_TDRE))
246 out_be32(&base->data, c);
249 /* Test whether a character is in the RX buffer */
250 static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
252 if ((in_be32(&base->water) >> 24) == 0)
259 * Initialise the serial port with the given baudrate. The settings
260 * are always 8 data bits, no parity, 1 stop bit, no start bits.
262 static int _lpuart32_serial_init(struct lpuart_fsl *base)
266 ctrl = in_be32(&base->ctrl);
269 out_be32(&base->ctrl, ctrl);
271 out_be32(&base->modir, 0);
272 out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
274 out_be32(&base->match, 0);
276 /* provide data bits, parity, stop bit, etc */
277 _lpuart32_serial_setbrg(base, gd->baudrate);
279 out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
284 #ifndef CONFIG_DM_SERIAL
285 static void lpuart32_serial_setbrg(void)
287 _lpuart32_serial_setbrg(base, gd->baudrate);
290 static int lpuart32_serial_getc(void)
292 return _lpuart32_serial_getc(base);
295 static void lpuart32_serial_putc(const char c)
297 _lpuart32_serial_putc(base, c);
300 static int lpuart32_serial_tstc(void)
302 return _lpuart32_serial_tstc(base);
305 static int lpuart32_serial_init(void)
307 return _lpuart32_serial_init(base);
310 static struct serial_device lpuart32_serial_drv = {
311 .name = "lpuart32_serial",
312 .start = lpuart32_serial_init,
314 .setbrg = lpuart32_serial_setbrg,
315 .putc = lpuart32_serial_putc,
316 .puts = default_serial_puts,
317 .getc = lpuart32_serial_getc,
318 .tstc = lpuart32_serial_tstc,
320 #else /* CONFIG_DM_SERIAL */
321 static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
323 struct lpuart_serial_platdata *plat = dev->platdata;
324 struct lpuart_fsl *reg = plat->reg;
326 _lpuart32_serial_setbrg(reg, baudrate);
331 static int lpuart32_serial_getc(struct udevice *dev)
333 struct lpuart_serial_platdata *plat = dev->platdata;
334 struct lpuart_fsl *reg = plat->reg;
336 return _lpuart32_serial_getc(reg);
339 static int lpuart32_serial_putc(struct udevice *dev, const char c)
341 struct lpuart_serial_platdata *plat = dev->platdata;
342 struct lpuart_fsl *reg = plat->reg;
344 _lpuart32_serial_putc(reg, c);
349 static int lpuart32_serial_pending(struct udevice *dev, bool input)
351 struct lpuart_serial_platdata *plat = dev->platdata;
352 struct lpuart_fsl *reg = plat->reg;
355 return _lpuart32_serial_tstc(reg);
357 return in_be32(®->stat) & STAT_TDRE ? 0 : 1;
360 static int lpuart32_serial_probe(struct udevice *dev)
362 struct lpuart_serial_platdata *plat = dev->platdata;
363 struct lpuart_fsl *reg = plat->reg;
365 return _lpuart32_serial_init(reg);
367 #endif /* CONFIG_DM_SERIAL */
370 #ifndef CONFIG_DM_SERIAL
371 void lpuart_serial_initialize(void)
373 #ifdef CONFIG_LPUART_32B_REG
374 serial_register(&lpuart32_serial_drv);
376 serial_register(&lpuart_serial_drv);
380 __weak struct serial_device *default_serial_console(void)
382 #ifdef CONFIG_LPUART_32B_REG
383 return &lpuart32_serial_drv;
385 return &lpuart_serial_drv;
388 #else /* CONFIG_DM_SERIAL */
389 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
391 struct lpuart_serial_platdata *plat = dev->platdata;
394 addr = dev_get_addr(dev);
395 if (addr == FDT_ADDR_T_NONE)
398 plat->reg = (struct lpuart_fsl *)addr;
403 #ifndef CONFIG_LPUART_32B_REG
404 static const struct dm_serial_ops lpuart_serial_ops = {
405 .putc = lpuart_serial_putc,
406 .pending = lpuart_serial_pending,
407 .getc = lpuart_serial_getc,
408 .setbrg = lpuart_serial_setbrg,
411 static const struct udevice_id lpuart_serial_ids[] = {
412 { .compatible = "fsl,vf610-lpuart" },
416 U_BOOT_DRIVER(serial_lpuart) = {
417 .name = "serial_lpuart",
419 .of_match = lpuart_serial_ids,
420 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
421 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
422 .probe = lpuart_serial_probe,
423 .ops = &lpuart_serial_ops,
424 .flags = DM_FLAG_PRE_RELOC,
426 #else /* CONFIG_LPUART_32B_REG */
427 static const struct dm_serial_ops lpuart32_serial_ops = {
428 .putc = lpuart32_serial_putc,
429 .pending = lpuart32_serial_pending,
430 .getc = lpuart32_serial_getc,
431 .setbrg = lpuart32_serial_setbrg,
434 static const struct udevice_id lpuart32_serial_ids[] = {
435 { .compatible = "fsl,ls1021a-lpuart" },
439 U_BOOT_DRIVER(serial_lpuart32) = {
440 .name = "serial_lpuart32",
442 .of_match = lpuart32_serial_ids,
443 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
444 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
445 .probe = lpuart32_serial_probe,
446 .ops = &lpuart32_serial_ops,
447 .flags = DM_FLAG_PRE_RELOC,
449 #endif /* CONFIG_LPUART_32B_REG */
450 #endif /* CONFIG_DM_SERIAL */