2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
16 #define US1_TDRE (1 << 7)
17 #define US1_RDRF (1 << 5)
18 #define US1_OR (1 << 3)
19 #define UC2_TE (1 << 3)
20 #define UC2_RE (1 << 2)
21 #define CFIFO_TXFLUSH (1 << 7)
22 #define CFIFO_RXFLUSH (1 << 6)
23 #define SFIFO_RXOF (1 << 2)
24 #define SFIFO_RXUF (1 << 0)
26 #define STAT_LBKDIF (1 << 31)
27 #define STAT_RXEDGIF (1 << 30)
28 #define STAT_TDRE (1 << 23)
29 #define STAT_RDRF (1 << 21)
30 #define STAT_IDLE (1 << 20)
31 #define STAT_OR (1 << 19)
32 #define STAT_NF (1 << 18)
33 #define STAT_FE (1 << 17)
34 #define STAT_PF (1 << 16)
35 #define STAT_MA1F (1 << 15)
36 #define STAT_MA2F (1 << 14)
37 #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
38 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
40 #define CTRL_TE (1 << 19)
41 #define CTRL_RE (1 << 18)
43 #define FIFO_TXFE 0x80
44 #define FIFO_RXFE 0x40
46 #define WATER_TXWATER_OFF 1
47 #define WATER_RXWATER_OFF 16
49 DECLARE_GLOBAL_DATA_PTR;
51 struct lpuart_serial_platdata {
52 struct lpuart_fsl *reg;
55 #ifndef CONFIG_LPUART_32B_REG
56 static void _lpuart_serial_setbrg(struct lpuart_fsl *base, int baudrate)
58 u32 clk = mxc_get_clock(MXC_UART_CLK);
61 sbr = (u16)(clk / (16 * baudrate));
63 /* place adjustment later - n/32 BRFA */
64 __raw_writeb(sbr >> 8, &base->ubdh);
65 __raw_writeb(sbr & 0xff, &base->ubdl);
68 static int _lpuart_serial_getc(struct lpuart_fsl *base)
70 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
75 return __raw_readb(&base->ud);
78 static void _lpuart_serial_putc(struct lpuart_fsl *base, const char c)
81 _lpuart_serial_putc(base, '\r');
83 while (!(__raw_readb(&base->us1) & US1_TDRE))
86 __raw_writeb(c, &base->ud);
89 /* Test whether a character is in the RX buffer */
90 static int _lpuart_serial_tstc(struct lpuart_fsl *base)
92 if (__raw_readb(&base->urcfifo) == 0)
99 * Initialise the serial port with the given baudrate. The settings
100 * are always 8 data bits, no parity, 1 stop bit, no start bits.
102 static int _lpuart_serial_init(struct lpuart_fsl *base)
106 ctrl = __raw_readb(&base->uc2);
109 __raw_writeb(ctrl, &base->uc2);
111 __raw_writeb(0, &base->umodem);
112 __raw_writeb(0, &base->uc1);
114 /* Disable FIFO and flush buffer */
115 __raw_writeb(0x0, &base->upfifo);
116 __raw_writeb(0x0, &base->utwfifo);
117 __raw_writeb(0x1, &base->urwfifo);
118 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
120 /* provide data bits, parity, stop bit, etc */
121 _lpuart_serial_setbrg(base, gd->baudrate);
123 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
128 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
130 struct lpuart_serial_platdata *plat = dev->platdata;
131 struct lpuart_fsl *reg = plat->reg;
133 _lpuart_serial_setbrg(reg, baudrate);
138 static int lpuart_serial_getc(struct udevice *dev)
140 struct lpuart_serial_platdata *plat = dev->platdata;
141 struct lpuart_fsl *reg = plat->reg;
143 return _lpuart_serial_getc(reg);
146 static int lpuart_serial_putc(struct udevice *dev, const char c)
148 struct lpuart_serial_platdata *plat = dev->platdata;
149 struct lpuart_fsl *reg = plat->reg;
151 _lpuart_serial_putc(reg, c);
156 static int lpuart_serial_pending(struct udevice *dev, bool input)
158 struct lpuart_serial_platdata *plat = dev->platdata;
159 struct lpuart_fsl *reg = plat->reg;
162 return _lpuart_serial_tstc(reg);
164 return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
167 static int lpuart_serial_probe(struct udevice *dev)
169 struct lpuart_serial_platdata *plat = dev->platdata;
170 struct lpuart_fsl *reg = plat->reg;
172 return _lpuart_serial_init(reg);
176 static void _lpuart32_serial_setbrg(struct lpuart_fsl *base, int baudrate)
178 u32 clk = CONFIG_SYS_CLK_FREQ;
181 sbr = (clk / (16 * baudrate));
183 /* place adjustment later - n/32 BRFA */
184 out_be32(&base->baud, sbr);
187 static int _lpuart32_serial_getc(struct lpuart_fsl *base)
191 while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
192 out_be32(&base->stat, STAT_FLAGS);
196 return in_be32(&base->data) & 0x3ff;
199 static void _lpuart32_serial_putc(struct lpuart_fsl *base, const char c)
202 _lpuart32_serial_putc(base, '\r');
204 while (!(in_be32(&base->stat) & STAT_TDRE))
207 out_be32(&base->data, c);
210 /* Test whether a character is in the RX buffer */
211 static int _lpuart32_serial_tstc(struct lpuart_fsl *base)
213 if ((in_be32(&base->water) >> 24) == 0)
220 * Initialise the serial port with the given baudrate. The settings
221 * are always 8 data bits, no parity, 1 stop bit, no start bits.
223 static int _lpuart32_serial_init(struct lpuart_fsl *base)
227 ctrl = in_be32(&base->ctrl);
230 out_be32(&base->ctrl, ctrl);
232 out_be32(&base->modir, 0);
233 out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
235 out_be32(&base->match, 0);
237 /* provide data bits, parity, stop bit, etc */
238 _lpuart32_serial_setbrg(base, gd->baudrate);
240 out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
245 static int lpuart32_serial_setbrg(struct udevice *dev, int baudrate)
247 struct lpuart_serial_platdata *plat = dev->platdata;
248 struct lpuart_fsl *reg = plat->reg;
250 _lpuart32_serial_setbrg(reg, baudrate);
255 static int lpuart32_serial_getc(struct udevice *dev)
257 struct lpuart_serial_platdata *plat = dev->platdata;
258 struct lpuart_fsl *reg = plat->reg;
260 return _lpuart32_serial_getc(reg);
263 static int lpuart32_serial_putc(struct udevice *dev, const char c)
265 struct lpuart_serial_platdata *plat = dev->platdata;
266 struct lpuart_fsl *reg = plat->reg;
268 _lpuart32_serial_putc(reg, c);
273 static int lpuart32_serial_pending(struct udevice *dev, bool input)
275 struct lpuart_serial_platdata *plat = dev->platdata;
276 struct lpuart_fsl *reg = plat->reg;
279 return _lpuart32_serial_tstc(reg);
281 return in_be32(®->stat) & STAT_TDRE ? 0 : 1;
284 static int lpuart32_serial_probe(struct udevice *dev)
286 struct lpuart_serial_platdata *plat = dev->platdata;
287 struct lpuart_fsl *reg = plat->reg;
289 return _lpuart32_serial_init(reg);
291 #endif /* CONFIG_LPUART_32B_REG */
293 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
295 struct lpuart_serial_platdata *plat = dev->platdata;
298 addr = dev_get_addr(dev);
299 if (addr == FDT_ADDR_T_NONE)
302 plat->reg = (struct lpuart_fsl *)addr;
307 #ifndef CONFIG_LPUART_32B_REG
308 static const struct dm_serial_ops lpuart_serial_ops = {
309 .putc = lpuart_serial_putc,
310 .pending = lpuart_serial_pending,
311 .getc = lpuart_serial_getc,
312 .setbrg = lpuart_serial_setbrg,
315 static const struct udevice_id lpuart_serial_ids[] = {
316 { .compatible = "fsl,vf610-lpuart" },
320 U_BOOT_DRIVER(serial_lpuart) = {
321 .name = "serial_lpuart",
323 .of_match = lpuart_serial_ids,
324 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
325 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
326 .probe = lpuart_serial_probe,
327 .ops = &lpuart_serial_ops,
328 .flags = DM_FLAG_PRE_RELOC,
330 #else /* CONFIG_LPUART_32B_REG */
331 static const struct dm_serial_ops lpuart32_serial_ops = {
332 .putc = lpuart32_serial_putc,
333 .pending = lpuart32_serial_pending,
334 .getc = lpuart32_serial_getc,
335 .setbrg = lpuart32_serial_setbrg,
338 static const struct udevice_id lpuart32_serial_ids[] = {
339 { .compatible = "fsl,ls1021a-lpuart" },
343 U_BOOT_DRIVER(serial_lpuart32) = {
344 .name = "serial_lpuart32",
346 .of_match = lpuart32_serial_ids,
347 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
348 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
349 .probe = lpuart32_serial_probe,
350 .ops = &lpuart32_serial_ops,
351 .flags = DM_FLAG_PRE_RELOC,
353 #endif /* CONFIG_LPUART_32B_REG */