3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
24 #ifndef CONFIG_DM_SERIAL
26 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
27 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
28 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
31 DECLARE_GLOBAL_DATA_PTR;
34 static int pl01x_putc(struct pl01x_regs *regs, char c)
36 /* Wait until there is space in the FIFO */
37 if (readl(®s->fr) & UART_PL01x_FR_TXFF)
40 /* Send the character */
46 static int pl01x_getc(struct pl01x_regs *regs)
50 /* Wait until there is data in the FIFO */
51 if (readl(®s->fr) & UART_PL01x_FR_RXFE)
54 data = readl(®s->dr);
56 /* Check for an error flag */
57 if (data & 0xFFFFFF00) {
59 writel(0xFFFFFFFF, ®s->ecr);
66 static int pl01x_tstc(struct pl01x_regs *regs)
69 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
77 /* disable everything */
78 writel(0, ®s->pl010_cr);
81 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
82 /* Empty RX fifo if necessary */
83 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
84 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
88 /* disable everything */
89 writel(0, ®s->pl011_cr);
98 static int pl011_set_line_control(struct pl01x_regs *regs)
102 * Internal update of baud rate register require line
103 * control register write
105 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
106 #ifdef CONFIG_PL011_SERIAL_RLCR
111 * Program receive line control register after waiting
112 * 10 bus cycles. Delay be writing to readonly register
115 for (i = 0; i < 10; i++)
116 writel(lcr, ®s->fr);
118 writel(lcr, ®s->pl011_rlcr);
121 writel(lcr, ®s->pl011_lcrh);
125 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
126 int clock, int baudrate)
130 unsigned int divisor;
132 /* disable everything */
133 writel(0, ®s->pl010_cr);
137 divisor = UART_PL010_BAUD_9600;
140 divisor = UART_PL010_BAUD_9600;
143 divisor = UART_PL010_BAUD_38400;
146 divisor = UART_PL010_BAUD_57600;
149 divisor = UART_PL010_BAUD_115200;
152 divisor = UART_PL010_BAUD_38400;
155 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
156 writel(divisor & 0xff, ®s->pl010_lcrl);
159 * Set line control for the PL010 to be 8 bits, 1 stop bit,
160 * no parity, fifo enabled
162 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
164 /* Finally, enable the UART */
165 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
170 unsigned int divider;
171 unsigned int remainder;
172 unsigned int fraction;
177 * IBRD = UART_CLK / (16 * BAUD_RATE)
178 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
179 * / (16 * BAUD_RATE))
181 temp = 16 * baudrate;
182 divider = clock / temp;
183 remainder = clock % temp;
184 temp = (8 * remainder) / baudrate;
185 fraction = (temp >> 1) + (temp & 1);
187 writel(divider, ®s->pl011_ibrd);
188 writel(fraction, ®s->pl011_fbrd);
190 pl011_set_line_control(regs);
191 /* Finally, enable the UART */
192 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
193 UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
203 #ifndef CONFIG_DM_SERIAL
204 static void pl01x_serial_init_baud(int baudrate)
208 #if defined(CONFIG_PL010_SERIAL)
209 pl01x_type = TYPE_PL010;
210 #elif defined(CONFIG_PL011_SERIAL)
211 pl01x_type = TYPE_PL011;
212 clock = CONFIG_PL011_CLOCK;
214 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
216 pl01x_generic_serial_init(base_regs, pl01x_type);
217 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
221 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
222 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
223 * Versatile PB has four UARTs.
225 int pl01x_serial_init(void)
227 pl01x_serial_init_baud(CONFIG_BAUDRATE);
232 static void pl01x_serial_putc(const char c)
235 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
237 while (pl01x_putc(base_regs, c) == -EAGAIN);
240 static int pl01x_serial_getc(void)
243 int ch = pl01x_getc(base_regs);
254 static int pl01x_serial_tstc(void)
256 return pl01x_tstc(base_regs);
259 static void pl01x_serial_setbrg(void)
262 * Flush FIFO and wait for non-busy before changing baudrate to avoid
265 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
267 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
269 pl01x_serial_init_baud(gd->baudrate);
272 static struct serial_device pl01x_serial_drv = {
273 .name = "pl01x_serial",
274 .start = pl01x_serial_init,
276 .setbrg = pl01x_serial_setbrg,
277 .putc = pl01x_serial_putc,
278 .puts = default_serial_puts,
279 .getc = pl01x_serial_getc,
280 .tstc = pl01x_serial_tstc,
283 void pl01x_serial_initialize(void)
285 serial_register(&pl01x_serial_drv);
288 __weak struct serial_device *default_serial_console(void)
290 return &pl01x_serial_drv;
293 #endif /* nCONFIG_DM_SERIAL */
295 #ifdef CONFIG_DM_SERIAL
298 struct pl01x_regs *regs;
299 enum pl01x_type type;
302 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
304 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
305 struct pl01x_priv *priv = dev_get_priv(dev);
307 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
312 static int pl01x_serial_probe(struct udevice *dev)
314 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
315 struct pl01x_priv *priv = dev_get_priv(dev);
317 priv->regs = (struct pl01x_regs *)plat->base;
318 priv->type = plat->type;
319 return pl01x_generic_serial_init(priv->regs, priv->type);
322 static int pl01x_serial_getc(struct udevice *dev)
324 struct pl01x_priv *priv = dev_get_priv(dev);
326 return pl01x_getc(priv->regs);
329 static int pl01x_serial_putc(struct udevice *dev, const char ch)
331 struct pl01x_priv *priv = dev_get_priv(dev);
333 return pl01x_putc(priv->regs, ch);
336 static int pl01x_serial_pending(struct udevice *dev, bool input)
338 struct pl01x_priv *priv = dev_get_priv(dev);
339 unsigned int fr = readl(&priv->regs->fr);
342 return pl01x_tstc(priv->regs);
344 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
347 static const struct dm_serial_ops pl01x_serial_ops = {
348 .putc = pl01x_serial_putc,
349 .pending = pl01x_serial_pending,
350 .getc = pl01x_serial_getc,
351 .setbrg = pl01x_serial_setbrg,
354 U_BOOT_DRIVER(serial_pl01x) = {
355 .name = "serial_pl01x",
357 .probe = pl01x_serial_probe,
358 .ops = &pl01x_serial_ops,
359 .flags = DM_FLAG_PRE_RELOC,
360 .priv_auto_alloc_size = sizeof(struct pl01x_priv),