git.sur5r.net Git - u-boot/blob - drivers/serial/serial_pl01x.c

   1 /*
   2  * (C) Copyright 2000
   3  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   4  *
   5  * (C) Copyright 2004
   6  * ARM Ltd.
   7  * Philippe Robin, <philippe.robin@arm.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  13
  14 #include <common.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <watchdog.h>
  18 #include <asm/io.h>
  19 #include <serial.h>
  20 #include <dm/platform_data/serial_pl01x.h>
  21 #include <linux/compiler.h>
  22 #include "serial_pl01x_internal.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #ifndef CONFIG_DM_SERIAL
  27
  28 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  29 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  30 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  31 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  32
  33 #endif
  34
  35 static int pl01x_putc(struct pl01x_regs *regs, char c)
  36 {
  37         /* Wait until there is space in the FIFO */
  38         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  39                 return -EAGAIN;
  40
  41         /* Send the character */
  42         writel(c, &regs->dr);
  43
  44         return 0;
  45 }
  46
  47 static int pl01x_getc(struct pl01x_regs *regs)
  48 {
  49         unsigned int data;
  50
  51         /* Wait until there is data in the FIFO */
  52         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  53                 return -EAGAIN;
  54
  55         data = readl(&regs->dr);
  56
  57         /* Check for an error flag */
  58         if (data & 0xFFFFFF00) {
  59                 /* Clear the error */
  60                 writel(0xFFFFFFFF, &regs->ecr);
  61                 return -1;
  62         }
  63
  64         return (int) data;
  65 }
  66
  67 static int pl01x_tstc(struct pl01x_regs *regs)
  68 {
  69         WATCHDOG_RESET();
  70         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  71 }
  72
  73 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  74                                      enum pl01x_type type)
  75 {
  76         switch (type) {
  77         case TYPE_PL010:
  78                 /* disable everything */
  79                 writel(0, &regs->pl010_cr);
  80                 break;
  81         case TYPE_PL011:
  82                 /* disable everything */
  83                 writel(0, &regs->pl011_cr);
  84                 break;
  85         default:
  86                 return -EINVAL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static int pl011_set_line_control(struct pl01x_regs *regs)
  93 {
  94         unsigned int lcr;
  95         /*
  96          * Internal update of baud rate register require line
  97          * control register write
  98          */
  99         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 100         writel(lcr, &regs->pl011_lcrh);
 101         return 0;
 102 }
 103
 104 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 105                                 int clock, int baudrate)
 106 {
 107         switch (type) {
 108         case TYPE_PL010: {
 109                 unsigned int divisor;
 110
 111                 /* disable everything */
 112                 writel(0, &regs->pl010_cr);
 113
 114                 switch (baudrate) {
 115                 case 9600:
 116                         divisor = UART_PL010_BAUD_9600;
 117                         break;
 118                 case 19200:
 119                         divisor = UART_PL010_BAUD_19200;
 120                         break;
 121                 case 38400:
 122                         divisor = UART_PL010_BAUD_38400;
 123                         break;
 124                 case 57600:
 125                         divisor = UART_PL010_BAUD_57600;
 126                         break;
 127                 case 115200:
 128                         divisor = UART_PL010_BAUD_115200;
 129                         break;
 130                 default:
 131                         divisor = UART_PL010_BAUD_38400;
 132                 }
 133
 134                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 135                 writel(divisor & 0xff, &regs->pl010_lcrl);
 136
 137                 /*
 138                  * Set line control for the PL010 to be 8 bits, 1 stop bit,
 139                  * no parity, fifo enabled
 140                  */
 141                 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 142                        &regs->pl010_lcrh);
 143                 /* Finally, enable the UART */
 144                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 145                 break;
 146         }
 147         case TYPE_PL011: {
 148                 unsigned int temp;
 149                 unsigned int divider;
 150                 unsigned int remainder;
 151                 unsigned int fraction;
 152
 153                 /*
 154                 * Set baud rate
 155                 *
 156                 * IBRD = UART_CLK / (16 * BAUD_RATE)
 157                 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 158                 *               / (16 * BAUD_RATE))
 159                 */
 160                 temp = 16 * baudrate;
 161                 divider = clock / temp;
 162                 remainder = clock % temp;
 163                 temp = (8 * remainder) / baudrate;
 164                 fraction = (temp >> 1) + (temp & 1);
 165
 166                 writel(divider, &regs->pl011_ibrd);
 167                 writel(fraction, &regs->pl011_fbrd);
 168
 169                 pl011_set_line_control(regs);
 170                 /* Finally, enable the UART */
 171                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 172                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 173                 break;
 174         }
 175         default:
 176                 return -EINVAL;
 177         }
 178
 179         return 0;
 180 }
 181
 182 #ifndef CONFIG_DM_SERIAL
 183 static void pl01x_serial_init_baud(int baudrate)
 184 {
 185         int clock = 0;
 186
 187 #if defined(CONFIG_PL010_SERIAL)
 188         pl01x_type = TYPE_PL010;
 189 #elif defined(CONFIG_PL011_SERIAL)
 190         pl01x_type = TYPE_PL011;
 191         clock = CONFIG_PL011_CLOCK;
 192 #endif
 193         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 194
 195         pl01x_generic_serial_init(base_regs, pl01x_type);
 196         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 197 }
 198
 199 /*
 200  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 201  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 202  * Versatile PB has four UARTs.
 203  */
 204 int pl01x_serial_init(void)
 205 {
 206         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 207
 208         return 0;
 209 }
 210
 211 static void pl01x_serial_putc(const char c)
 212 {
 213         if (c == '\n')
 214                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 215
 216         while (pl01x_putc(base_regs, c) == -EAGAIN);
 217 }
 218
 219 static int pl01x_serial_getc(void)
 220 {
 221         while (1) {
 222                 int ch = pl01x_getc(base_regs);
 223
 224                 if (ch == -EAGAIN) {
 225                         WATCHDOG_RESET();
 226                         continue;
 227                 }
 228
 229                 return ch;
 230         }
 231 }
 232
 233 static int pl01x_serial_tstc(void)
 234 {
 235         return pl01x_tstc(base_regs);
 236 }
 237
 238 static void pl01x_serial_setbrg(void)
 239 {
 240         /*
 241          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 242          * crap in console
 243          */
 244         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 245                 WATCHDOG_RESET();
 246         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 247                 WATCHDOG_RESET();
 248         pl01x_serial_init_baud(gd->baudrate);
 249 }
 250
 251 static struct serial_device pl01x_serial_drv = {
 252         .name   = "pl01x_serial",
 253         .start  = pl01x_serial_init,
 254         .stop   = NULL,
 255         .setbrg = pl01x_serial_setbrg,
 256         .putc   = pl01x_serial_putc,
 257         .puts   = default_serial_puts,
 258         .getc   = pl01x_serial_getc,
 259         .tstc   = pl01x_serial_tstc,
 260 };
 261
 262 void pl01x_serial_initialize(void)
 263 {
 264         serial_register(&pl01x_serial_drv);
 265 }
 266
 267 __weak struct serial_device *default_serial_console(void)
 268 {
 269         return &pl01x_serial_drv;
 270 }
 271
 272 #endif /* nCONFIG_DM_SERIAL */
 273
 274 #ifdef CONFIG_DM_SERIAL
 275
 276 struct pl01x_priv {
 277         struct pl01x_regs *regs;
 278         enum pl01x_type type;
 279 };
 280
 281 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 282 {
 283         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 284         struct pl01x_priv *priv = dev_get_priv(dev);
 285
 286         if (!plat->skip_init) {
 287                 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 288                                      baudrate);
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int pl01x_serial_probe(struct udevice *dev)
 295 {
 296         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 297         struct pl01x_priv *priv = dev_get_priv(dev);
 298
 299         priv->regs = (struct pl01x_regs *)plat->base;
 300         priv->type = plat->type;
 301         if (!plat->skip_init)
 302                 return pl01x_generic_serial_init(priv->regs, priv->type);
 303         else
 304                 return 0;
 305 }
 306
 307 static int pl01x_serial_getc(struct udevice *dev)
 308 {
 309         struct pl01x_priv *priv = dev_get_priv(dev);
 310
 311         return pl01x_getc(priv->regs);
 312 }
 313
 314 static int pl01x_serial_putc(struct udevice *dev, const char ch)
 315 {
 316         struct pl01x_priv *priv = dev_get_priv(dev);
 317
 318         return pl01x_putc(priv->regs, ch);
 319 }
 320
 321 static int pl01x_serial_pending(struct udevice *dev, bool input)
 322 {
 323         struct pl01x_priv *priv = dev_get_priv(dev);
 324         unsigned int fr = readl(&priv->regs->fr);
 325
 326         if (input)
 327                 return pl01x_tstc(priv->regs);
 328         else
 329                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 330 }
 331
 332 static const struct dm_serial_ops pl01x_serial_ops = {
 333         .putc = pl01x_serial_putc,
 334         .pending = pl01x_serial_pending,
 335         .getc = pl01x_serial_getc,
 336         .setbrg = pl01x_serial_setbrg,
 337 };
 338
 339 #if CONFIG_IS_ENABLED(OF_CONTROL)
 340 static const struct udevice_id pl01x_serial_id[] ={
 341         {.compatible = "arm,pl011", .data = TYPE_PL011},
 342         {.compatible = "arm,pl010", .data = TYPE_PL010},
 343         {}
 344 };
 345
 346 static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
 347 {
 348         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 349         fdt_addr_t addr;
 350
 351         addr = devfdt_get_addr(dev);
 352         if (addr == FDT_ADDR_T_NONE)
 353                 return -EINVAL;
 354
 355         plat->base = addr;
 356         plat->clock = dev_read_u32_default(dev, "clock", 1);
 357         plat->type = dev_get_driver_data(dev);
 358         plat->skip_init = dev_read_bool(dev, "skip-init");
 359
 360         return 0;
 361 }
 362 #endif
 363
 364 U_BOOT_DRIVER(serial_pl01x) = {
 365         .name   = "serial_pl01x",
 366         .id     = UCLASS_SERIAL,
 367         .of_match = of_match_ptr(pl01x_serial_id),
 368         .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
 369         .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
 370         .probe = pl01x_serial_probe,
 371         .ops    = &pl01x_serial_ops,
 372         .flags = DM_FLAG_PRE_RELOC,
 373         .priv_auto_alloc_size = sizeof(struct pl01x_priv),
 374 };
 375
 376 #endif
 377
 378 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 379
 380 #include <debug_uart.h>
 381
 382 static void _debug_uart_init(void)
 383 {
 384 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 385         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 386         enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
 387                                 TYPE_PL011 : TYPE_PL010;
 388
 389         pl01x_generic_serial_init(regs, type);
 390         pl01x_generic_setbrg(regs, type,
 391                              CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 392 #endif
 393 }
 394
 395 static inline void _debug_uart_putc(int ch)
 396 {
 397         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 398
 399         pl01x_putc(regs, ch);
 400 }
 401
 402 DEBUG_UART_FUNCS
 403
 404 #endif