3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
24 #ifndef CONFIG_DM_SERIAL
26 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
27 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
28 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
29 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
31 DECLARE_GLOBAL_DATA_PTR;
34 static int pl01x_putc(struct pl01x_regs *regs, char c)
36 /* Wait until there is space in the FIFO */
37 if (readl(®s->fr) & UART_PL01x_FR_TXFF)
40 /* Send the character */
46 static int pl01x_getc(struct pl01x_regs *regs)
50 /* Wait until there is data in the FIFO */
51 if (readl(®s->fr) & UART_PL01x_FR_RXFE)
54 data = readl(®s->dr);
56 /* Check for an error flag */
57 if (data & 0xFFFFFF00) {
59 writel(0xFFFFFFFF, ®s->ecr);
66 static int pl01x_tstc(struct pl01x_regs *regs)
69 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
77 /* disable everything */
78 writel(0, ®s->pl010_cr);
81 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
82 /* Empty RX fifo if necessary */
83 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
84 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
88 /* disable everything */
89 writel(0, ®s->pl011_cr);
98 static int set_line_control(struct pl01x_regs *regs)
102 * Internal update of baud rate register require line
103 * control register write
105 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
106 #ifdef CONFIG_PL011_SERIAL_RLCR
111 * Program receive line control register after waiting
112 * 10 bus cycles. Delay be writing to readonly register
115 for (i = 0; i < 10; i++)
116 writel(lcr, ®s->fr);
118 writel(lcr, ®s->pl011_rlcr);
121 writel(lcr, ®s->pl011_lcrh);
125 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
126 int clock, int baudrate)
130 unsigned int divisor;
134 divisor = UART_PL010_BAUD_9600;
137 divisor = UART_PL010_BAUD_9600;
140 divisor = UART_PL010_BAUD_38400;
143 divisor = UART_PL010_BAUD_57600;
146 divisor = UART_PL010_BAUD_115200;
149 divisor = UART_PL010_BAUD_38400;
152 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
153 writel(divisor & 0xff, ®s->pl010_lcrl);
155 /* Finally, enable the UART */
156 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
161 unsigned int divider;
162 unsigned int remainder;
163 unsigned int fraction;
168 * IBRD = UART_CLK / (16 * BAUD_RATE)
169 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
170 * / (16 * BAUD_RATE))
172 temp = 16 * baudrate;
173 divider = clock / temp;
174 remainder = clock % temp;
175 temp = (8 * remainder) / baudrate;
176 fraction = (temp >> 1) + (temp & 1);
178 writel(divider, ®s->pl011_ibrd);
179 writel(fraction, ®s->pl011_fbrd);
181 set_line_control(regs);
182 /* Finally, enable the UART */
183 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
184 UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
194 #ifndef CONFIG_DM_SERIAL
195 static void pl01x_serial_init_baud(int baudrate)
199 #if defined(CONFIG_PL010_SERIAL)
200 pl01x_type = TYPE_PL010;
201 #elif defined(CONFIG_PL011_SERIAL)
202 pl01x_type = TYPE_PL011;
203 clock = CONFIG_PL011_CLOCK;
205 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
207 pl01x_generic_serial_init(base_regs, pl01x_type);
208 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
212 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
213 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
214 * Versatile PB has four UARTs.
216 int pl01x_serial_init(void)
218 pl01x_serial_init_baud(CONFIG_BAUDRATE);
223 static void pl01x_serial_putc(const char c)
226 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
228 while (pl01x_putc(base_regs, c) == -EAGAIN);
231 static int pl01x_serial_getc(void)
234 int ch = pl01x_getc(base_regs);
245 static int pl01x_serial_tstc(void)
247 return pl01x_tstc(base_regs);
250 static void pl01x_serial_setbrg(void)
253 * Flush FIFO and wait for non-busy before changing baudrate to avoid
256 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
258 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
260 pl01x_serial_init_baud(gd->baudrate);
263 static struct serial_device pl01x_serial_drv = {
264 .name = "pl01x_serial",
265 .start = pl01x_serial_init,
267 .setbrg = pl01x_serial_setbrg,
268 .putc = pl01x_serial_putc,
269 .puts = default_serial_puts,
270 .getc = pl01x_serial_getc,
271 .tstc = pl01x_serial_tstc,
274 void pl01x_serial_initialize(void)
276 serial_register(&pl01x_serial_drv);
279 __weak struct serial_device *default_serial_console(void)
281 return &pl01x_serial_drv;
284 #endif /* nCONFIG_DM_SERIAL */
286 #ifdef CONFIG_DM_SERIAL
289 struct pl01x_regs *regs;
290 enum pl01x_type type;
293 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
295 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
296 struct pl01x_priv *priv = dev_get_priv(dev);
298 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
303 static int pl01x_serial_probe(struct udevice *dev)
305 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
306 struct pl01x_priv *priv = dev_get_priv(dev);
308 priv->regs = (struct pl01x_regs *)plat->base;
309 priv->type = plat->type;
310 return pl01x_generic_serial_init(priv->regs, priv->type);
313 static int pl01x_serial_getc(struct udevice *dev)
315 struct pl01x_priv *priv = dev_get_priv(dev);
317 return pl01x_getc(priv->regs);
320 static int pl01x_serial_putc(struct udevice *dev, const char ch)
322 struct pl01x_priv *priv = dev_get_priv(dev);
324 return pl01x_putc(priv->regs, ch);
327 static int pl01x_serial_pending(struct udevice *dev, bool input)
329 struct pl01x_priv *priv = dev_get_priv(dev);
330 unsigned int fr = readl(&priv->regs->fr);
333 return pl01x_tstc(priv->regs);
335 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
338 static const struct dm_serial_ops pl01x_serial_ops = {
339 .putc = pl01x_serial_putc,
340 .pending = pl01x_serial_pending,
341 .getc = pl01x_serial_getc,
342 .setbrg = pl01x_serial_setbrg,
345 U_BOOT_DRIVER(serial_pl01x) = {
346 .name = "serial_pl01x",
348 .probe = pl01x_serial_probe,
349 .ops = &pl01x_serial_ops,
350 .flags = DM_FLAG_PRE_RELOC,
351 .priv_auto_alloc_size = sizeof(struct pl01x_priv),