1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
10 #define CR1_OFFSET(x) (x ? 0x0c : 0x00)
11 #define CR3_OFFSET(x) (x ? 0x14 : 0x08)
12 #define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
13 #define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
15 #define ICR_OFFSET 0x20
17 * STM32F4 has one Data Register (DR) for received or transmitted
18 * data, so map Receive Data Register (RDR) and Transmit Data
19 * Register (TDR) at the same offset
21 #define RDR_OFFSET(x) (x ? 0x04 : 0x24)
22 #define TDR_OFFSET(x) (x ? 0x04 : 0x28)
24 struct stm32_uart_info {
25 u8 uart_enable_bit; /* UART_CR1_UE */
26 bool stm32f4; /* true for STM32F4, false otherwise */
30 struct stm32_uart_info stm32f4_info = {
32 .uart_enable_bit = 13,
36 struct stm32_uart_info stm32f7_info = {
42 struct stm32_uart_info stm32h7_info = {
48 /* Information about a serial port */
49 struct stm32x7_serial_platdata {
50 fdt_addr_t base; /* address of registers in physical memory */
51 struct stm32_uart_info *uart_info;
52 unsigned long int clock_rate;
55 #define USART_CR1_FIFOEN BIT(29)
56 #define USART_CR1_OVER8 BIT(15)
57 #define USART_CR1_TE BIT(3)
58 #define USART_CR1_RE BIT(2)
60 #define USART_CR3_OVRDIS BIT(12)
62 #define USART_ISR_FLAG_ORE BIT(3)
63 #define USART_ISR_FLAG_RXNE BIT(5)
64 #define USART_ISR_FLAG_TXE BIT(7)
66 #define USART_BRR_F_MASK GENMASK(7, 0)
67 #define USART_BRR_M_SHIFT 4
68 #define USART_BRR_M_MASK GENMASK(15, 4)
70 #define USART_ICR_OREF BIT(3)