2 * TI serdes driver for keystone2.
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/ti-common/keystone_serdes.h>
14 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
15 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
16 #define SERDES_COMLANE_REGS 0x0a00
17 #define SERDES_WIZ_REGS 0x1fc0
19 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
20 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
21 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
22 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
23 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
24 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
25 #define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
27 #define SERDES_RESET BIT(28)
28 #define SERDES_LANE_RESET BIT(29)
29 #define SERDES_LANE_LOOPBACK BIT(30)
30 #define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
32 #define SERDES_CMU_CFG_NUM 5
33 #define SERDES_COMLANE_CFG_NUM 10
34 #define SERDES_LANE_CFG_NUM 10
43 enum ks2_serdes_clock clk;
44 enum ks2_serdes_rate rate;
45 struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
46 struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
47 struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
50 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
51 static u32 serdes_cfg_lane_enable[] = {
52 0xf000f0c0, /* SGMII */
53 0xf0e9f038, /* PCSR */
56 /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
57 static u32 serdes_cfg_pll_enable[] = {
58 0xe0000000, /* SGMII */
59 0xee000000, /* PCSR */
63 * Array to hold all possible serdes configurations.
64 * Combination for 5 clock settings and 6 baud rates.
66 static struct cfg_entry cfgs[] = {
68 .clk = SERDES_CLOCK_156P25M,
69 .rate = SERDES_RATE_5G,
71 {0x0000, 0x00800000, 0xffff0000},
72 {0x0014, 0x00008282, 0x0000ffff},
73 {0x0060, 0x00142438, 0x00ffffff},
74 {0x0064, 0x00c3c700, 0x00ffff00},
75 {0x0078, 0x0000c000, 0x0000ff00}
78 {0x0a00, 0x00000800, 0x0000ff00},
79 {0x0a08, 0x38a20000, 0xffff0000},
80 {0x0a30, 0x008a8a00, 0x00ffff00},
81 {0x0a84, 0x00000600, 0x0000ff00},
82 {0x0a94, 0x10000000, 0xff000000},
83 {0x0aa0, 0x81000000, 0xff000000},
84 {0x0abc, 0xff000000, 0xff000000},
85 {0x0ac0, 0x0000008b, 0x000000ff},
86 {0x0b08, 0x583f0000, 0xffff0000},
87 {0x0b0c, 0x0000004e, 0x000000ff}
90 {0x0004, 0x38000080, 0xff0000ff},
91 {0x0008, 0x00000000, 0x000000ff},
92 {0x000c, 0x02000000, 0xff000000},
93 {0x0010, 0x1b000000, 0xff000000},
94 {0x0014, 0x00006fb8, 0x0000ffff},
95 {0x0018, 0x758000e4, 0xffff00ff},
96 {0x00ac, 0x00004400, 0x0000ff00},
97 {0x002c, 0x00100800, 0x00ffff00},
98 {0x0080, 0x00820082, 0x00ff00ff},
99 {0x0084, 0x1d0f0385, 0xffffffff}
104 static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
106 writel(((readl(addr) & (~mask)) | (value & mask)), addr);
109 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
113 for (i = 0; i < size; i++)
114 ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
117 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
122 for (i = 0; i < size; i++)
123 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
124 cfg_lane[i].val, cfg_lane[i].mask);
127 static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
131 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
132 ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
134 for (i = 0; i < num_lanes; i++)
135 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
140 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
142 /* Bring SerDes out of Reset */
143 ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
144 if (serdes->intf == SERDES_PHY_PCSR)
145 ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
147 /* Enable CMU and COMLANE */
148 ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
149 if (serdes->intf == SERDES_PHY_PCSR)
150 ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
152 ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
155 static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
157 writel(serdes_cfg_pll_enable[serdes->intf],
158 base + SERDES_PLL_CTL_REG);
161 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
164 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
165 0x1, SERDES_LANE_RESET);
167 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
168 0x0, SERDES_LANE_RESET);
171 static void ks2_serdes_lane_enable(u32 base,
172 struct ks2_serdes *serdes, u32 lane)
174 /* Bring lane out of reset */
175 ks2_serdes_lane_reset(base, 0, lane);
177 writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
179 base + SERDES_LANE_CTL_STATUS_REG(lane));
181 /* Set NES bit if Loopback Enabled */
182 if (serdes->loopback)
183 ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
184 0x1, SERDES_LANE_LOOPBACK);
187 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
192 for (i = 0; i < ARRAY_SIZE(cfgs); i++)
193 if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
196 if (i >= ARRAY_SIZE(cfgs)) {
197 puts("Cannot find keystone SerDes configuration");
201 ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
203 ks2_serdes_cmu_comlane_enable(base, serdes);
204 for (i = 0; i < num_lanes; i++)
205 ks2_serdes_lane_enable(base, serdes, i);
207 ks2_serdes_pll_enable(base, serdes);