2 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 * Copyright 2011 Maxim Integrated Products
6 * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <asm/arch/clk.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/power.h>
29 struct max98095_priv {
30 enum max98095_type devtype;
36 static struct sound_codec_info g_codec_info;
37 struct max98095_priv g_max98095_info;
38 unsigned int g_max98095_i2c_dev_addr;
40 /* Index 0 is reserved. */
41 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
45 * Writes value to a device register through i2c
47 * @param reg reg number to be write
48 * @param data data to be writen to the above registor
50 * @return int value 1 for change, 0 for no change or negative error code.
52 static int max98095_i2c_write(unsigned int reg, unsigned char data)
54 debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n",
56 return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1);
60 * Read a value from a device register through i2c
62 * @param reg reg number to be read
63 * @param data address of read data to be stored
65 * @return int value 0 for success, -1 in case of error.
67 static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data)
71 ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1);
73 debug("%s: Error while reading register %#04x\n",
82 * update device register bits through i2c
84 * @param reg codec register
85 * @param mask register mask
86 * @param value new value
88 * @return int value 0 for success, non-zero error code.
90 static int max98095_update_bits(unsigned int reg, unsigned char mask,
94 unsigned char old, new;
96 if (max98095_i2c_read(reg, &old) != 0)
98 new = (old & ~mask) | (value & mask);
99 change = (old != new) ? 1 : 0;
101 ret = max98095_i2c_write(reg, new);
109 * codec mclk clock divider coefficients based on sampling rate
111 * @param rate sampling rate
112 * @param value address of indexvalue to be stored
114 * @return 0 for success or negative error code.
116 static int rate_value(int rate, u8 *value)
120 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
121 if (rate_table[i] >= rate) {
132 * Sets hw params for max98095
134 * @param max98095 max98095 information pointer
135 * @param rate Sampling rate
136 * @param bits_per_sample Bits per sample
138 * @return -1 for error and 0 Success.
140 static int max98095_hw_params(struct max98095_priv *max98095,
141 unsigned int rate, unsigned int bits_per_sample)
146 switch (bits_per_sample) {
148 error = max98095_update_bits(M98095_034_DAI2_FORMAT,
152 error = max98095_update_bits(M98095_034_DAI2_FORMAT,
153 M98095_DAI_WS, M98095_DAI_WS);
156 debug("%s: Illegal bits per sample %d.\n",
157 __func__, bits_per_sample);
161 if (rate_value(rate, ®val)) {
162 debug("%s: Failed to set sample rate to %d.\n",
166 max98095->rate = rate;
168 error |= max98095_update_bits(M98095_031_DAI2_CLKMODE,
169 M98095_CLKMODE_MASK, regval);
171 /* Update sample rate mode */
173 error |= max98095_update_bits(M98095_038_DAI2_FILTERS,
176 error |= max98095_update_bits(M98095_038_DAI2_FILTERS,
177 M98095_DAI_DHF, M98095_DAI_DHF);
180 debug("%s: Error setting hardware params.\n", __func__);
188 * Configures Audio interface system clock for the given frequency
190 * @param max98095 max98095 information
191 * @param freq Sampling frequency in Hz
193 * @return -1 for error and 0 success.
195 static int max98095_set_sysclk(struct max98095_priv *max98095,
200 /* Requested clock frequency is already setup */
201 if (freq == max98095->sysclk)
204 /* Setup clocks for slave mode, and using the PLL
205 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
206 * 0x02 (when master clk is 20MHz to 40MHz)..
207 * 0x03 (when master clk is 40MHz to 60MHz)..
209 if ((freq >= 10000000) && (freq < 20000000)) {
210 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10);
211 } else if ((freq >= 20000000) && (freq < 40000000)) {
212 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20);
213 } else if ((freq >= 40000000) && (freq < 60000000)) {
214 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30);
216 debug("%s: Invalid master clock frequency\n", __func__);
220 debug("%s: Clock at %uHz\n", __func__, freq);
225 max98095->sysclk = freq;
230 * Sets Max98095 I2S format
232 * @param max98095 max98095 information
233 * @param fmt i2S format - supports a subset of the options defined
236 * @return -1 for error and 0 Success.
238 static int max98095_set_fmt(struct max98095_priv *max98095, int fmt)
243 if (fmt == max98095->fmt)
248 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249 case SND_SOC_DAIFMT_CBS_CFS:
251 error |= max98095_i2c_write(M98095_032_DAI2_CLKCFG_HI,
253 error |= max98095_i2c_write(M98095_033_DAI2_CLKCFG_LO,
256 case SND_SOC_DAIFMT_CBM_CFM:
257 /* Set to master mode */
258 regval |= M98095_DAI_MAS;
260 case SND_SOC_DAIFMT_CBS_CFM:
261 case SND_SOC_DAIFMT_CBM_CFS:
263 debug("%s: Clock mode unsupported\n", __func__);
267 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
268 case SND_SOC_DAIFMT_I2S:
269 regval |= M98095_DAI_DLY;
271 case SND_SOC_DAIFMT_LEFT_J:
274 debug("%s: Unrecognized format.\n", __func__);
278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
279 case SND_SOC_DAIFMT_NB_NF:
281 case SND_SOC_DAIFMT_NB_IF:
282 regval |= M98095_DAI_WCI;
284 case SND_SOC_DAIFMT_IB_NF:
285 regval |= M98095_DAI_BCI;
287 case SND_SOC_DAIFMT_IB_IF:
288 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
291 debug("%s: Unrecognized inversion settings.\n", __func__);
295 error |= max98095_update_bits(M98095_034_DAI2_FORMAT,
296 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI |
297 M98095_DAI_WCI, regval);
299 error |= max98095_i2c_write(M98095_035_DAI2_CLOCK,
303 debug("%s: Error setting i2s format.\n", __func__);
311 * resets the audio codec
313 * @return -1 for error and 0 success.
315 static int max98095_reset(void)
320 * Gracefully reset the DSP core and the codec hardware in a proper
323 ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0);
325 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
329 ret = max98095_i2c_write(M98095_097_PWR_SYS, 0);
331 debug("%s: Failed to reset codec: %d\n", __func__, ret);
336 * Reset to hardware default for registers, as there is not a soft
337 * reset hardware control register.
339 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
340 ret = max98095_i2c_write(i, 0);
342 debug("%s: Failed to reset: %d\n", __func__, ret);
351 * Intialise max98095 codec device
353 * @param max98095 max98095 information
355 * @returns -1 for error and 0 Success.
357 static int max98095_device_init(struct max98095_priv *max98095)
362 /* reset the codec, the DSP core, and disable all interrupts */
363 error = max98095_reset();
369 /* initialize private data */
370 max98095->sysclk = -1U;
371 max98095->rate = -1U;
374 error = max98095_i2c_read(M98095_0FF_REV_ID, &id);
376 debug("%s: Failure reading hardware revision: %d\n",
380 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
382 error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV);
385 * initialize registers to hardware default configuring audio
388 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
389 M98095_DAI2M_TO_DACL|M98095_DAI2M_TO_DACR);
391 error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
392 M98095_SPK_SPREADSPECTRUM);
393 error |= max98095_i2c_write(M98095_045_CFG_DSP, M98095_DSPNORMAL);
394 error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
396 error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
397 M98095_S1NORMAL|M98095_SDATA);
399 error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
400 M98095_S2NORMAL|M98095_SDATA);
402 error |= max98095_i2c_write(M98095_040_DAI3_IOCFG,
403 M98095_S3NORMAL|M98095_SDATA);
405 /* take the codec out of the shut down */
406 error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
408 /* route DACL and DACR output to HO and Spekers */
409 error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */
410 error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */
411 error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */
412 error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */
415 error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3);
418 error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15);
419 error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15);
420 error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16);
421 error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16);
424 error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
425 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
434 static int max98095_do_init(struct sound_codec_info *pcodec_info,
435 int sampling_rate, int mclk_freq,
440 /* Enable codec clock */
443 /* shift the device address by 1 for 7 bit addressing */
444 g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1;
446 if (pcodec_info->codec_type == CODEC_MAX_98095)
447 g_max98095_info.devtype = MAX98095;
449 debug("%s: Codec id [%d] not defined\n", __func__,
450 pcodec_info->codec_type);
454 ret = max98095_device_init(&g_max98095_info);
456 debug("%s: max98095 codec chip init failed\n", __func__);
460 ret = max98095_set_sysclk(&g_max98095_info, mclk_freq);
462 debug("%s: max98095 codec set sys clock failed\n", __func__);
466 ret = max98095_hw_params(&g_max98095_info, sampling_rate,
470 ret = max98095_set_fmt(&g_max98095_info,
472 SND_SOC_DAIFMT_NB_NF |
473 SND_SOC_DAIFMT_CBS_CFS);
479 static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
483 #ifdef CONFIG_OF_CONTROL
484 enum fdt_compat_id compat;
488 /* Get the node from FDT for codec */
489 node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
491 debug("EXYNOS_SOUND: No node for codec in device tree\n");
492 debug("node = %d\n", node);
496 parent = fdt_parent_offset(blob, node);
498 debug("%s: Cannot find node parent\n", __func__);
502 compat = fdtdec_lookup(blob, parent);
504 case COMPAT_SAMSUNG_S3C2440_I2C:
505 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
506 error |= pcodec_info->i2c_bus;
507 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
508 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
510 error |= pcodec_info->i2c_dev_addr;
511 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
514 debug("%s: Unknown compat id %d\n", __func__, compat);
518 pcodec_info->i2c_bus = AUDIO_I2C_BUS;
519 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
520 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
522 pcodec_info->codec_type = CODEC_MAX_98095;
524 debug("fail to get max98095 codec node properties\n");
531 /* max98095 Device Initialisation */
532 int max98095_init(const void *blob, int sampling_rate, int mclk_freq,
536 int old_bus = i2c_get_bus_num();
537 struct sound_codec_info *pcodec_info = &g_codec_info;
539 if (get_max98095_codec_values(pcodec_info, blob) < 0) {
540 debug("FDT Codec values failed\n");
544 i2c_set_bus_num(pcodec_info->i2c_bus);
545 ret = max98095_do_init(pcodec_info, sampling_rate, mclk_freq,
547 i2c_set_bus_num(old_bus);