1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
7 #include <asm/arch/clk.h>
8 #include <asm/arch/pinmux.h>
9 #include <asm/arch/i2s-regs.h>
15 #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
16 #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
17 #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
18 #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
19 #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
21 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
24 * Sets the frame size for I2S LR clock
26 * @param i2s_reg i2s regiter address
27 * @param rfs Frame Size
29 static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
31 unsigned int mod = readl(&i2s_reg->mod);
33 mod &= ~MOD_RCLK_MASK;
37 mod |= MOD_RCLK_768FS;
40 mod |= MOD_RCLK_512FS;
43 mod |= MOD_RCLK_384FS;
46 mod |= MOD_RCLK_256FS;
50 writel(mod, &i2s_reg->mod);
54 * Sets the i2s transfer control
56 * @param i2s_reg i2s regiter address
57 * @param on 1 enable tx , 0 disable tx transfer
59 static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
61 unsigned int con = readl(&i2s_reg->con);
62 unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
66 con &= ~CON_TXCH_PAUSE;
68 con |= CON_TXCH_PAUSE;
72 writel(mod, &i2s_reg->mod);
73 writel(con, &i2s_reg->con);
77 * set the bit clock frame size (in multiples of LRCLK)
79 * @param i2s_reg i2s regiter address
80 * @param bfs bit Frame Size
82 static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
84 unsigned int mod = readl(&i2s_reg->mod);
86 mod &= ~MOD_BCLK_MASK;
104 writel(mod, &i2s_reg->mod);
108 * flushes the i2stx fifo
110 * @param i2s_reg i2s regiter address
111 * @param flush Tx fifo flush command (0x00 - do not flush
112 * 0x80 - flush tx fifo)
114 void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
117 setbits_le32(&i2s_reg->fic, flush);
118 clrbits_le32(&i2s_reg->fic, flush);
122 * Set System Clock direction
124 * @param i2s_reg i2s regiter address
125 * @param dir Clock direction
127 * @return int value 0 for success, -1 in case of error
129 int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
131 unsigned int mod = readl(&i2s_reg->mod);
133 if (dir == SND_SOC_CLOCK_IN)
136 mod &= ~MOD_CDCLKCON;
138 writel(mod, &i2s_reg->mod);
144 * Sets I2S Clcok format
146 * @param fmt i2s clock properties
147 * @param i2s_reg i2s regiter address
149 * @return int value 0 for success, -1 in case of error
151 int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
153 unsigned int mod = readl(&i2s_reg->mod);
154 unsigned int tmp = 0;
155 unsigned int ret = 0;
157 /* Format is priority */
158 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
159 case SND_SOC_DAIFMT_RIGHT_J:
163 case SND_SOC_DAIFMT_LEFT_J:
167 case SND_SOC_DAIFMT_I2S:
171 debug("%s: Invalid format priority [0x%x]\n", __func__,
172 (fmt & SND_SOC_DAIFMT_FORMAT_MASK));
177 * INV flag is relative to the FORMAT flag - if set it simply
178 * flips the polarity specified by the Standard
180 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
181 case SND_SOC_DAIFMT_NB_NF:
183 case SND_SOC_DAIFMT_NB_IF:
184 if (tmp & MOD_LR_RLOW)
190 debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
191 (fmt & SND_SOC_DAIFMT_INV_MASK));
195 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
196 case SND_SOC_DAIFMT_CBS_CFS:
199 case SND_SOC_DAIFMT_CBM_CFM:
200 /* Set default source clock in Master mode */
201 ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
203 debug("%s:set i2s clock direction failed\n", __func__);
208 debug("%s: Invalid master selection [0x%x]\n", __func__,
209 (fmt & SND_SOC_DAIFMT_MASTER_MASK));
213 mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
215 writel(mod, &i2s_reg->mod);
221 * Sets the sample width in bits
223 * @param blc samplewidth (size of sample in bits)
224 * @param i2s_reg i2s regiter address
226 * @return int value 0 for success, -1 in case of error
228 int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
230 unsigned int mod = readl(&i2s_reg->mod);
232 mod &= ~MOD_BLCP_MASK;
233 mod &= ~MOD_BLC_MASK;
237 mod |= MOD_BLCP_8BIT;
241 mod |= MOD_BLCP_16BIT;
242 mod |= MOD_BLC_16BIT;
245 mod |= MOD_BLCP_24BIT;
246 mod |= MOD_BLC_24BIT;
249 debug("%s: Invalid sample size input [0x%x]\n",
253 writel(mod, &i2s_reg->mod);
258 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
259 unsigned long data_size)
263 struct i2s_reg *i2s_reg =
264 (struct i2s_reg *)pi2s_tx->base_address;
266 if (data_size < FIFO_LENGTH) {
267 debug("%s : Invalid data size\n", __func__);
268 return -1; /* invalid pcm data size */
271 /* fill the tx buffer before stating the tx transmit */
272 for (i = 0; i < FIFO_LENGTH; i++)
273 writel(*data++, &i2s_reg->txd);
275 data_size -= FIFO_LENGTH;
276 i2s_txctrl(i2s_reg, I2S_TX_ON);
278 while (data_size > 0) {
279 start = get_timer(0);
280 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
281 writel(*data++, &i2s_reg->txd);
284 if (get_timer(start) > TIMEOUT_I2S_TX) {
285 i2s_txctrl(i2s_reg, I2S_TX_OFF);
286 debug("%s: I2S Transfer Timeout\n", __func__);
291 i2s_txctrl(i2s_reg, I2S_TX_OFF);
296 int i2s_tx_init(struct i2stx_info *pi2s_tx)
299 struct i2s_reg *i2s_reg =
300 (struct i2s_reg *)pi2s_tx->base_address;
301 if (pi2s_tx->id == 0) {
302 /* Initialize GPIO for I2S-0 */
303 exynos_pinmux_config(PERIPH_ID_I2S0, 0);
306 ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
307 } else if (pi2s_tx->id == 1) {
308 /* Initialize GPIO for I2S-1 */
309 exynos_pinmux_config(PERIPH_ID_I2S1, 0);
312 ret = set_epll_clk(pi2s_tx->audio_pll_clk);
314 debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
319 debug("%s: epll clock set rate failed\n", __func__);
323 /* Select Clk Source for Audio 0 or 1 */
324 ret = set_i2s_clk_source(pi2s_tx->id);
326 debug("%s: unsupported clock for i2s-%d\n", __func__,
331 if (pi2s_tx->id == 0) {
332 /*Reset the i2s module */
333 writel(CON_RESET, &i2s_reg->con);
335 writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
336 /* set i2s prescaler */
337 writel(PSREN | PSVAL, &i2s_reg->psr);
339 /* Set Prescaler to get MCLK */
340 ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
341 (pi2s_tx->samplingrate * (pi2s_tx->rfs)),
345 debug("%s: unsupported prescalar for i2s-%d\n", __func__,
350 /* Configure I2s format */
351 ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
352 SND_SOC_DAIFMT_CBM_CFM));
354 i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
355 ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
357 debug("%s:set sample rate failed\n", __func__);
361 i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
362 /* disable i2s transfer flag and flush the fifo */
363 i2s_txctrl(i2s_reg, I2S_TX_OFF);
364 i2s_fifo(i2s_reg, FIC_TXFLUSH);
366 debug("%s: failed\n", __func__);