2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chandrasekar <rcsekar@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clk.h>
9 #include <asm/arch/pinmux.h>
10 #include <asm/arch/i2s-regs.h>
16 #define FIC_TX2COUNT(x) (((x) >> 24) & 0xf)
17 #define FIC_TX1COUNT(x) (((x) >> 16) & 0xf)
18 #define FIC_TXCOUNT(x) (((x) >> 8) & 0xf)
19 #define FIC_RXCOUNT(x) (((x) >> 0) & 0xf)
20 #define FICS_TXCOUNT(x) (((x) >> 8) & 0x7f)
22 #define TIMEOUT_I2S_TX 100 /* i2s transfer timeout */
25 * Sets the frame size for I2S LR clock
27 * @param i2s_reg i2s regiter address
28 * @param rfs Frame Size
30 static void i2s_set_lr_framesize(struct i2s_reg *i2s_reg, unsigned int rfs)
32 unsigned int mod = readl(&i2s_reg->mod);
34 mod &= ~MOD_RCLK_MASK;
38 mod |= MOD_RCLK_768FS;
41 mod |= MOD_RCLK_512FS;
44 mod |= MOD_RCLK_384FS;
47 mod |= MOD_RCLK_256FS;
51 writel(mod, &i2s_reg->mod);
55 * Sets the i2s transfer control
57 * @param i2s_reg i2s regiter address
58 * @param on 1 enable tx , 0 disable tx transfer
60 static void i2s_txctrl(struct i2s_reg *i2s_reg, int on)
62 unsigned int con = readl(&i2s_reg->con);
63 unsigned int mod = readl(&i2s_reg->mod) & ~MOD_MASK;
67 con &= ~CON_TXCH_PAUSE;
71 con |= CON_TXCH_PAUSE;
75 writel(mod, &i2s_reg->mod);
76 writel(con, &i2s_reg->con);
80 * set the bit clock frame size (in multiples of LRCLK)
82 * @param i2s_reg i2s regiter address
83 * @param bfs bit Frame Size
85 static void i2s_set_bitclk_framesize(struct i2s_reg *i2s_reg, unsigned bfs)
87 unsigned int mod = readl(&i2s_reg->mod);
89 mod &= ~MOD_BCLK_MASK;
102 mod |= MOD_BCLK_16FS;
107 writel(mod, &i2s_reg->mod);
111 * flushes the i2stx fifo
113 * @param i2s_reg i2s regiter address
114 * @param flush Tx fifo flush command (0x00 - do not flush
115 * 0x80 - flush tx fifo)
117 void i2s_fifo(struct i2s_reg *i2s_reg, unsigned int flush)
120 setbits_le32(&i2s_reg->fic, flush);
121 clrbits_le32(&i2s_reg->fic, flush);
125 * Set System Clock direction
127 * @param i2s_reg i2s regiter address
128 * @param dir Clock direction
130 * @return int value 0 for success, -1 in case of error
132 int i2s_set_sysclk_dir(struct i2s_reg *i2s_reg, int dir)
134 unsigned int mod = readl(&i2s_reg->mod);
136 if (dir == SND_SOC_CLOCK_IN)
139 mod &= ~MOD_CDCLKCON;
141 writel(mod, &i2s_reg->mod);
147 * Sets I2S Clcok format
149 * @param fmt i2s clock properties
150 * @param i2s_reg i2s regiter address
152 * @return int value 0 for success, -1 in case of error
154 int i2s_set_fmt(struct i2s_reg *i2s_reg, unsigned int fmt)
156 unsigned int mod = readl(&i2s_reg->mod);
157 unsigned int tmp = 0;
158 unsigned int ret = 0;
160 /* Format is priority */
161 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
162 case SND_SOC_DAIFMT_RIGHT_J:
166 case SND_SOC_DAIFMT_LEFT_J:
170 case SND_SOC_DAIFMT_I2S:
174 debug("%s: Invalid format priority [0x%x]\n", __func__,
175 (fmt & SND_SOC_DAIFMT_FORMAT_MASK));
180 * INV flag is relative to the FORMAT flag - if set it simply
181 * flips the polarity specified by the Standard
183 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
184 case SND_SOC_DAIFMT_NB_NF:
186 case SND_SOC_DAIFMT_NB_IF:
187 if (tmp & MOD_LR_RLOW)
193 debug("%s: Invalid clock ploarity input [0x%x]\n", __func__,
194 (fmt & SND_SOC_DAIFMT_INV_MASK));
198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199 case SND_SOC_DAIFMT_CBS_CFS:
202 case SND_SOC_DAIFMT_CBM_CFM:
203 /* Set default source clock in Master mode */
204 ret = i2s_set_sysclk_dir(i2s_reg, SND_SOC_CLOCK_OUT);
206 debug("%s:set i2s clock direction failed\n", __func__);
211 debug("%s: Invalid master selection [0x%x]\n", __func__,
212 (fmt & SND_SOC_DAIFMT_MASTER_MASK));
216 mod &= ~(MOD_SDF_MASK | MOD_LR_RLOW | MOD_SLAVE);
218 writel(mod, &i2s_reg->mod);
224 * Sets the sample width in bits
226 * @param blc samplewidth (size of sample in bits)
227 * @param i2s_reg i2s regiter address
229 * @return int value 0 for success, -1 in case of error
231 int i2s_set_samplesize(struct i2s_reg *i2s_reg, unsigned int blc)
233 unsigned int mod = readl(&i2s_reg->mod);
235 mod &= ~MOD_BLCP_MASK;
236 mod &= ~MOD_BLC_MASK;
240 mod |= MOD_BLCP_8BIT;
244 mod |= MOD_BLCP_16BIT;
245 mod |= MOD_BLC_16BIT;
248 mod |= MOD_BLCP_24BIT;
249 mod |= MOD_BLC_24BIT;
252 debug("%s: Invalid sample size input [0x%x]\n",
256 writel(mod, &i2s_reg->mod);
261 int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data,
262 unsigned long data_size)
266 struct i2s_reg *i2s_reg =
267 (struct i2s_reg *)pi2s_tx->base_address;
269 if (data_size < FIFO_LENGTH) {
270 debug("%s : Invalid data size\n", __func__);
271 return -1; /* invalid pcm data size */
274 /* fill the tx buffer before stating the tx transmit */
275 for (i = 0; i < FIFO_LENGTH; i++)
276 writel(*data++, &i2s_reg->txd);
278 data_size -= FIFO_LENGTH;
279 i2s_txctrl(i2s_reg, I2S_TX_ON);
281 while (data_size > 0) {
282 start = get_timer(0);
283 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) {
284 writel(*data++, &i2s_reg->txd);
287 if (get_timer(start) > TIMEOUT_I2S_TX) {
288 i2s_txctrl(i2s_reg, I2S_TX_OFF);
289 debug("%s: I2S Transfer Timeout\n", __func__);
294 i2s_txctrl(i2s_reg, I2S_TX_OFF);
299 int i2s_tx_init(struct i2stx_info *pi2s_tx)
302 struct i2s_reg *i2s_reg =
303 (struct i2s_reg *)pi2s_tx->base_address;
305 /* Initialize GPIO for I2s */
306 exynos_pinmux_config(PERIPH_ID_I2S1, 0);
309 ret = set_epll_clk(pi2s_tx->audio_pll_clk);
311 debug("%s: epll clock set rate falied\n", __func__);
315 /* Select Clk Source for Audio1 */
316 set_i2s_clk_source();
318 /* Set Prescaler to get MCLK */
319 set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
320 (pi2s_tx->samplingrate * (pi2s_tx->rfs)));
322 /* Configure I2s format */
323 ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
324 SND_SOC_DAIFMT_CBM_CFM));
326 i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
327 ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
329 debug("%s:set sample rate failed\n", __func__);
333 i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
334 /* disable i2s transfer flag and flush the fifo */
335 i2s_txctrl(i2s_reg, I2S_TX_OFF);
336 i2s_fifo(i2s_reg, FIC_TXFLUSH);
338 debug("%s: failed\n", __func__);