1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
7 #include <asm/arch/clk.h>
8 #include <asm/arch/cpu.h>
16 #include <asm/arch/sound.h>
18 #include "wm8994_registers.h"
20 /* defines for wm8994 system clock selection */
21 #define SEL_MCLK1 0x00
22 #define SEL_MCLK2 0x08
26 /* fll config to configure fll */
27 struct wm8994_fll_config {
29 int in; /* Input frequency in Hz */
30 int out; /* output frequency in Hz */
33 /* codec private data */
35 enum wm8994_type type; /* codec type of wolfson */
36 int revision; /* Revision */
37 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
38 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
39 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
40 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
43 /* wm 8994 supported sampling rate values */
44 static unsigned int src_rate[] = {
45 8000, 11025, 12000, 16000, 22050, 24000,
46 32000, 44100, 48000, 88200, 96000
49 /* op clock divisions */
50 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
52 /* lr clock frame size ratio */
53 static int fs_ratios[] = {
54 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
57 /* bit clock divisors */
58 static int bclk_divs[] = {
59 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
60 640, 880, 960, 1280, 1760, 1920
63 static struct wm8994_priv g_wm8994_info;
64 static unsigned char g_wm8994_i2c_dev_addr;
65 static struct sound_codec_info g_codec_info;
68 * Initialise I2C for wm 8994
70 * @param bus no i2c bus number in which wm8994 is connected
72 static void wm8994_i2c_init(int bus_no)
74 i2c_set_bus_num(bus_no);
78 * Writes value to a device register through i2c
80 * @param reg reg number to be write
81 * @param data data to be writen to the above registor
83 * @return int value 1 for change, 0 for no change or negative error code.
85 static int wm8994_i2c_write(unsigned int reg, unsigned short data)
89 val[0] = (unsigned char)((data >> 8) & 0xff);
90 val[1] = (unsigned char)(data & 0xff);
91 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
93 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
97 * Read a value from a device register through i2c
99 * @param reg reg number to be read
100 * @param data address of read data to be stored
102 * @return int value 0 for success, -1 in case of error.
104 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
106 unsigned char val[2];
109 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
111 debug("%s: Error while reading register %#04x\n",
124 * update device register bits through i2c
126 * @param reg codec register
127 * @param mask register mask
128 * @param value new value
130 * @return int value 1 if change in the register value,
131 * 0 for no change or negative error code.
133 static int wm8994_update_bits(unsigned int reg, unsigned short mask,
134 unsigned short value)
136 int change , ret = 0;
137 unsigned short old, new;
139 if (wm8994_i2c_read(reg, &old) != 0)
141 new = (old & ~mask) | (value & mask);
142 change = (old != new) ? 1 : 0;
144 ret = wm8994_i2c_write(reg, new);
152 * Sets i2s set format
154 * @param aif_id Interface ID
155 * @param fmt i2S format
157 * @return -1 for error and 0 Success.
159 int wm8994_set_fmt(int aif_id, unsigned int fmt)
170 ms_reg = WM8994_AIF1_MASTER_SLAVE;
171 aif_reg = WM8994_AIF1_CONTROL_1;
172 aif_clk = WM8994_AIF1_CLOCKING_1;
175 ms_reg = WM8994_AIF2_MASTER_SLAVE;
176 aif_reg = WM8994_AIF2_CONTROL_1;
177 aif_clk = WM8994_AIF2_CLOCKING_1;
180 debug("%s: Invalid audio interface selection\n", __func__);
184 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
185 case SND_SOC_DAIFMT_CBS_CFS:
187 case SND_SOC_DAIFMT_CBM_CFM:
188 ms = WM8994_AIF1_MSTR;
191 debug("%s: Invalid i2s master selection\n", __func__);
195 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
196 case SND_SOC_DAIFMT_DSP_B:
197 aif |= WM8994_AIF1_LRCLK_INV;
198 case SND_SOC_DAIFMT_DSP_A:
201 case SND_SOC_DAIFMT_I2S:
204 case SND_SOC_DAIFMT_RIGHT_J:
206 case SND_SOC_DAIFMT_LEFT_J:
210 debug("%s: Invalid i2s format selection\n", __func__);
214 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
215 case SND_SOC_DAIFMT_DSP_A:
216 case SND_SOC_DAIFMT_DSP_B:
217 /* frame inversion not valid for DSP modes */
218 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
219 case SND_SOC_DAIFMT_NB_NF:
221 case SND_SOC_DAIFMT_IB_NF:
222 aif |= WM8994_AIF1_BCLK_INV;
225 debug("%s: Invalid i2s frame inverse selection\n",
231 case SND_SOC_DAIFMT_I2S:
232 case SND_SOC_DAIFMT_RIGHT_J:
233 case SND_SOC_DAIFMT_LEFT_J:
234 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
235 case SND_SOC_DAIFMT_NB_NF:
237 case SND_SOC_DAIFMT_IB_IF:
238 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
240 case SND_SOC_DAIFMT_IB_NF:
241 aif |= WM8994_AIF1_BCLK_INV;
243 case SND_SOC_DAIFMT_NB_IF:
244 aif |= WM8994_AIF1_LRCLK_INV;
247 debug("%s: Invalid i2s clock polarity selection\n",
253 debug("%s: Invalid i2s format selection\n", __func__);
257 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
258 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
260 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
261 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
264 debug("%s: codec register access error\n", __func__);
272 * Sets hw params FOR WM8994
274 * @param wm8994 wm8994 information pointer
275 * @param aif_id Audio interface ID
276 * @param sampling_rate Sampling rate
277 * @param bits_per_sample Bits per sample
278 * @param Channels Channels in the given audio input
280 * @return -1 for error and 0 Success.
282 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
283 unsigned int sampling_rate, unsigned int bits_per_sample,
284 unsigned int channels)
295 int i, cur_val, best_val, bclk_rate, best;
296 unsigned short reg_data;
301 aif1_reg = WM8994_AIF1_CONTROL_1;
302 aif2_reg = WM8994_AIF1_CONTROL_2;
303 bclk_reg = WM8994_AIF1_BCLK;
304 rate_reg = WM8994_AIF1_RATE;
307 aif1_reg = WM8994_AIF2_CONTROL_1;
308 aif2_reg = WM8994_AIF2_CONTROL_2;
309 bclk_reg = WM8994_AIF2_BCLK;
310 rate_reg = WM8994_AIF2_RATE;
316 bclk_rate = sampling_rate * 32;
317 switch (bits_per_sample) {
337 /* Try to find an appropriate sample rate; look for an exact match. */
338 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
339 if (src_rate[i] == sampling_rate)
342 if (i == ARRAY_SIZE(src_rate)) {
343 debug("%s: Could not get the best matching samplingrate\n",
348 rate_val |= i << WM8994_AIF1_SR_SHIFT;
350 /* AIFCLK/fs ratio; look for a close match in either direction */
352 best_val = abs((fs_ratios[0] * sampling_rate)
353 - wm8994->aifclk[id]);
355 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
356 cur_val = abs((fs_ratios[i] * sampling_rate)
357 - wm8994->aifclk[id]);
358 if (cur_val >= best_val)
367 * We may not get quite the right frequency if using
368 * approximate clocks so look for the closest match that is
369 * higher than the target (we need to ensure that there enough
370 * BCLKs to clock out the samples).
373 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
374 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
375 if (cur_val < 0) /* BCLK table is sorted */
380 if (i == ARRAY_SIZE(bclk_divs)) {
381 debug("%s: Could not get the best matching bclk division\n",
386 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
387 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
389 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
390 debug("%s: AIF1 register read Failed\n", __func__);
394 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
395 aif2 |= WM8994_AIF1_MONO;
397 if (wm8994->aifclk[id] == 0) {
398 debug("%s:Audio interface clock not set\n", __func__);
402 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
403 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
404 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
405 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
406 WM8994_AIF1CLK_RATE_MASK, rate_val);
408 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
411 debug("%s: codec register access error\n", __func__);
419 * Configures Audio interface Clock
421 * @param wm8994 wm8994 information pointer
422 * @param aif Audio Interface ID
424 * @return -1 for error and 0 Success.
426 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
433 /* AIF(1/0) register adress offset calculated */
439 switch (wm8994->sysclk[aif-1]) {
440 case WM8994_SYSCLK_MCLK1:
442 rate = wm8994->mclk[0];
445 case WM8994_SYSCLK_MCLK2:
447 rate = wm8994->mclk[1];
450 case WM8994_SYSCLK_FLL1:
452 rate = wm8994->fll[0].out;
455 case WM8994_SYSCLK_FLL2:
457 rate = wm8994->fll[1].out;
461 debug("%s: Invalid input clock selection [%d]\n",
462 __func__, wm8994->sysclk[aif-1]);
466 /* if input clock frequenct is more than 135Mhz then divide */
467 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
469 reg1 |= WM8994_AIF1CLK_DIV;
472 wm8994->aifclk[aif-1] = rate;
474 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
475 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
478 if (aif == WM8994_AIF1)
479 ret |= wm8994_update_bits(WM8994_CLOCKING_1,
480 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
481 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
482 else if (aif == WM8994_AIF2)
483 ret |= wm8994_update_bits(WM8994_CLOCKING_1,
484 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
485 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
486 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
489 debug("%s: codec register access error\n", __func__);
497 * Configures Audio interface for the given frequency
499 * @param wm8994 wm8994 information
500 * @param aif_id Audio Interface
501 * @param clk_id Input Clock ID
502 * @param freq Sampling frequency in Hz
504 * @return -1 for error and 0 success.
506 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
507 int clk_id, unsigned int freq)
512 wm8994->sysclk[aif_id - 1] = clk_id;
515 case WM8994_SYSCLK_MCLK1:
516 wm8994->mclk[0] = freq;
518 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
519 WM8994_AIF2DAC_DIV_MASK , 0);
523 case WM8994_SYSCLK_MCLK2:
524 /* TODO: Set GPIO AF */
525 wm8994->mclk[1] = freq;
528 case WM8994_SYSCLK_FLL1:
529 case WM8994_SYSCLK_FLL2:
532 case WM8994_SYSCLK_OPCLK:
534 * Special case - a division (times 10) is given and
535 * no effect on main clocking.
538 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
539 if (opclk_divs[i] == freq)
541 if (i == ARRAY_SIZE(opclk_divs)) {
542 debug("%s frequency divisor not found\n",
546 ret = wm8994_update_bits(WM8994_CLOCKING_2,
547 WM8994_OPCLK_DIV_MASK, i);
548 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
549 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
551 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
552 WM8994_OPCLK_ENA, 0);
556 debug("%s Invalid input clock selection [%d]\n",
561 ret |= configure_aif_clock(wm8994, aif_id);
564 debug("%s: codec register access error\n", __func__);
572 * Initializes Volume for AIF2 to HP path
574 * @returns -1 for error and 0 Success.
577 static int wm8994_init_volume_aif2_dac1(void)
582 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
583 WM8994_AIF2DAC_MUTE_MASK, 0);
586 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
587 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
588 WM8994_AIF2DAC_VU | 0xff);
590 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
591 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
592 WM8994_AIF2DAC_VU | 0xff);
595 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
596 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
597 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
599 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
600 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
601 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
602 /* Head Phone Volume */
603 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
604 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
607 debug("%s: codec register access error\n", __func__);
615 * Initializes Volume for AIF1 to HP path
617 * @returns -1 for error and 0 Success.
620 static int wm8994_init_volume_aif1_dac1(void)
625 ret |= wm8994_i2c_write(WM8994_AIF1_DAC_FILTERS_1, 0x0000);
627 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
628 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
629 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
631 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
632 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
633 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
634 /* Head Phone Volume */
635 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
636 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
639 debug("%s: codec register access error\n", __func__);
647 * Intialise wm8994 codec device
649 * @param wm8994 wm8994 information
651 * @returns -1 for error and 0 Success.
653 static int wm8994_device_init(struct wm8994_priv *wm8994,
654 enum en_audio_interface aif_id)
657 unsigned short reg_data;
660 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
662 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
664 debug("Failed to read ID register\n");
668 if (reg_data == WM8994_ID) {
670 debug("Device registered as type %d\n", wm8994->type);
671 wm8994->type = WM8994;
673 debug("Device is not a WM8994, ID is %x\n", ret);
678 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
680 debug("Failed to read revision register: %d\n", ret);
683 wm8994->revision = reg_data;
684 debug("%s revision %c\n", devname, 'A' + wm8994->revision);
687 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
688 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
690 /* Charge Pump Enable */
691 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
694 /* Head Phone Power Enable */
695 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
696 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
698 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
699 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
701 if (aif_id == WM8994_AIF1) {
702 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_2,
703 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
704 WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
707 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_4,
708 WM8994_ADCL_ENA | WM8994_ADCR_ENA |
709 WM8994_AIF1ADC1R_ENA |
710 WM8994_AIF1ADC1L_ENA);
712 /* Power enable for AIF1 and DAC1 */
713 ret |= wm8994_i2c_write(WM8994_POWER_MANAGEMENT_5,
714 WM8994_AIF1DACL_ENA |
715 WM8994_AIF1DACR_ENA |
716 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
717 } else if (aif_id == WM8994_AIF2) {
718 /* Power enable for AIF2 and DAC1 */
719 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
720 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
721 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
722 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
723 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
725 /* Head Phone Initialisation */
726 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
727 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
728 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
730 ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
731 WM8994_DCS_ENA_CHAN_0_MASK |
732 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
733 WM8994_DCS_ENA_CHAN_1);
735 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
736 WM8994_HPOUT1L_DLY_MASK |
737 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
738 WM8994_HPOUT1R_OUTP_MASK |
739 WM8994_HPOUT1L_RMV_SHORT_MASK |
740 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
741 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
742 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
743 WM8994_HPOUT1R_RMV_SHORT);
745 /* MIXER Config DAC1 to HP */
746 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
747 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
749 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
750 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
752 if (aif_id == WM8994_AIF1) {
753 /* Routing AIF1 to DAC1 */
754 ret |= wm8994_i2c_write(WM8994_DAC1_LEFT_MIXER_ROUTING,
755 WM8994_AIF1DAC1L_TO_DAC1L);
757 ret |= wm8994_i2c_write(WM8994_DAC1_RIGHT_MIXER_ROUTING,
758 WM8994_AIF1DAC1R_TO_DAC1R);
760 /* GPIO Settings for AIF1 */
761 ret |= wm8994_i2c_write(WM8994_GPIO_1, WM8994_GPIO_DIR_OUTPUT
762 | WM8994_GPIO_FUNCTION_I2S_CLK
763 | WM8994_GPIO_INPUT_DEBOUNCE);
765 ret |= wm8994_init_volume_aif1_dac1();
766 } else if (aif_id == WM8994_AIF2) {
767 /* Routing AIF2 to DAC1 */
768 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
769 WM8994_AIF2DACL_TO_DAC1L_MASK,
770 WM8994_AIF2DACL_TO_DAC1L);
772 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
773 WM8994_AIF2DACR_TO_DAC1R_MASK,
774 WM8994_AIF2DACR_TO_DAC1R);
776 /* GPIO Settings for AIF2 */
778 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
779 WM8994_GPIO_FUNCTION_MASK ,
780 WM8994_GPIO_DIR_OUTPUT);
783 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
784 WM8994_GPIO_FUNCTION_MASK,
785 WM8994_GPIO_DIR_OUTPUT);
788 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
789 WM8994_GPIO_FUNCTION_MASK,
790 WM8994_GPIO_DIR_OUTPUT);
792 ret |= wm8994_init_volume_aif2_dac1();
798 debug("%s: Codec chip init ok\n", __func__);
801 debug("%s: Codec chip init error\n", __func__);
806 * Gets fdt values for wm8994 config parameters
808 * @param pcodec_info codec information structure
809 * @param blob FDT blob
810 * @return int value, 0 for success
812 static int get_codec_values(struct sound_codec_info *pcodec_info,
816 #if CONFIG_IS_ENABLED(OF_CONTROL)
817 enum fdt_compat_id compat;
821 /* Get the node from FDT for codec */
822 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
824 debug("EXYNOS_SOUND: No node for codec in device tree\n");
825 debug("node = %d\n", node);
829 parent = fdt_parent_offset(blob, node);
831 debug("%s: Cannot find node parent\n", __func__);
835 compat = fdtdec_lookup(blob, parent);
837 case COMPAT_SAMSUNG_S3C2440_I2C:
838 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
839 error |= pcodec_info->i2c_bus;
840 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
841 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
843 error |= pcodec_info->i2c_dev_addr;
844 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
847 debug("%s: Unknown compat id %d\n", __func__, compat);
851 pcodec_info->i2c_bus = AUDIO_I2C_BUS;
852 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
853 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
856 pcodec_info->codec_type = CODEC_WM_8994;
859 debug("fail to get wm8994 codec node properties\n");
866 /* WM8994 Device Initialisation */
867 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
868 int sampling_rate, int mclk_freq,
869 int bits_per_sample, unsigned int channels)
872 struct sound_codec_info *pcodec_info = &g_codec_info;
874 /* Get the codec Values */
875 if (get_codec_values(pcodec_info, blob) < 0) {
876 debug("FDT Codec values failed\n");
880 /* shift the device address by 1 for 7 bit addressing */
881 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
882 wm8994_i2c_init(pcodec_info->i2c_bus);
884 if (pcodec_info->codec_type == CODEC_WM_8994) {
885 g_wm8994_info.type = WM8994;
887 debug("%s: Codec id [%d] not defined\n", __func__,
888 pcodec_info->codec_type);
892 ret = wm8994_device_init(&g_wm8994_info, aif_id);
894 debug("%s: wm8994 codec chip init failed\n", __func__);
898 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
901 debug("%s: wm8994 codec set sys clock failed\n", __func__);
905 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
906 bits_per_sample, channels);
909 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
910 SND_SOC_DAIFMT_NB_NF |
911 SND_SOC_DAIFMT_CBS_CFS);