4 bool "Enable Driver Model for SPI drivers"
7 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
19 bool "Cadence QSPI driver"
21 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
22 used to access the SPI NOR flash on platforms embedding this
26 bool "Designware SPI driver"
28 Enable the Designware SPI driver. This driver can be used to
29 access the SPI NOR flash on platforms embedding this Designware
33 bool "Samsung Exynos SPI driver"
35 Enable the Samsung Exynos SPI driver. This driver can be used to
36 access the SPI NOR flash on platforms embedding this Samsung
40 bool "Freescale DSPI driver"
42 Enable the Freescale DSPI driver. This driver can be used to
43 access the SPI NOR flash and SPI Data flash on platforms embedding
44 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
48 bool "Freescale QSPI driver"
50 Enable the Freescale Quad-SPI (QSPI) driver. This driver can be
51 used to access the SPI NOR flash on platforms embedding this
55 bool "Intel ICH SPI driver"
57 Enable the Intel ICH SPI driver. This driver can be used to
58 access the SPI NOR flash on platforms embedding this Intel
62 bool "Rockchip SPI driver"
64 Enable the Rockchip SPI driver, used to access SPI NOR flash and
65 other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
66 This uses driver model and requires a device tree binding to
70 bool "Sandbox SPI driver"
71 depends on SANDBOX && DM
73 Enable SPI support for sandbox. This is an emulation of a real SPI
74 bus. Devices can be attached to the bus using the device tree
75 which specifies the driver to use. As an example, see this device
76 tree fragment from sandbox.dts. It shows that the SPI bus has a
77 single flash device on chip select 0 which is emulated by the driver
78 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
84 compatible = "sandbox,spi";
85 cs-gpios = <0>, <&gpio_a 0>;
88 compatible = "spansion,m25p16", "sandbox,spi-flash";
89 spi-max-frequency = <40000000>;
90 sandbox,filename = "spi.bin";
95 bool "nVidia Tegra114 SPI driver"
97 Enable the nVidia Tegra114 SPI driver. This driver can be used to
98 access the SPI NOR flash on platforms embedding this nVidia Tegra114
101 This controller is different than the older SoCs SPI controller and
102 also register interface get changed with this controller.
104 config TEGRA20_SFLASH
105 bool "nVidia Tegra20 Serial Flash controller driver"
107 Enable the nVidia Tegra20 Serial Flash controller driver. This driver
108 can be used to access the SPI NOR flash on platforms embedding this
109 nVidia Tegra20 IP core.
112 bool "nVidia Tegra20/Tegra30 SLINK driver"
114 Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can
115 be used to access the SPI NOR flash on platforms embedding this
116 nVidia Tegra20/Tegra30 IP cores.
119 bool "Xilinx SPI driver"
121 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
122 controller support 8 bit SPI transfers only, with or w/o FIFO.
123 For more info on Xilinx SPI Register Definitions and Overview
124 see driver file - drivers/spi/xilinx_spi.c
127 bool "Zynq SPI driver"
128 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
130 Enable the Zynq SPI driver. This driver can be used to
131 access the SPI NOR flash on platforms embedding this Zynq
137 bool "Freescale eSPI driver"
139 Enable the Freescale eSPI driver. This driver can be used to
140 access the SPI interface and SPI NOR flash on platforms embedding
141 this Freescale eSPI IP core.
144 bool "TI QSPI driver"
146 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
147 This driver support spi flash single, quad and memory reads.
149 endmenu # menu "SPI Support"