2 * Driver for ATMEL DataFlash support
3 * Author : Hamid Ikdoumi (Atmel)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #ifndef CONFIG_AT91_LEGACY
24 # define CONFIG_ATMEL_LEGACY
25 # warning Please update to use C structure SoC access !
33 #include <asm/arch/clk.h>
34 #include <asm/arch/hardware.h>
36 #include "atmel_spi.h"
38 #include <asm/arch/gpio.h>
39 #include <asm/arch/at91_pio.h>
40 #include <asm/arch/at91_spi.h>
42 #include <dataflash.h>
44 #define AT91_SPI_PCS0_DATAFLASH_CARD 0xE /* Chip Select 0: NPCS0%1110 */
45 #define AT91_SPI_PCS1_DATAFLASH_CARD 0xD /* Chip Select 1: NPCS1%1101 */
46 #define AT91_SPI_PCS2_DATAFLASH_CARD 0xB /* Chip Select 2: NPCS2%1011 */
47 #define AT91_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3: NPCS3%0111 */
49 void AT91F_SpiInit(void)
52 writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
54 /* Configure SPI in Master Mode with No CS selected !!! */
55 writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
56 ATMEL_BASE_SPI0 + AT91_SPI_MR);
59 writel(AT91_SPI_NCPHA |
60 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
61 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
62 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
63 ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
65 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
67 writel(AT91_SPI_NCPHA |
68 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
69 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
70 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
71 ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
73 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
75 writel(AT91_SPI_NCPHA |
76 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
77 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
78 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
79 ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
81 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
83 writel(AT91_SPI_NCPHA |
84 (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
85 (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
86 ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
87 ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
91 writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
93 while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
97 * Add tempo to get SPI in a safe state.
98 * Should not be needed for new silicon (Rev B)
101 readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
102 readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
106 void AT91F_SpiEnable(int cs)
111 case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
112 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
114 writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
115 ATMEL_BASE_SPI0 + AT91_SPI_MR);
117 case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
118 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
120 writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
121 ATMEL_BASE_SPI0 + AT91_SPI_MR);
123 case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
124 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
126 writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
127 ATMEL_BASE_SPI0 + AT91_SPI_MR);
130 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
132 writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
133 ATMEL_BASE_SPI0 + AT91_SPI_MR);
138 writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
141 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
143 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
145 unsigned int timeout;
146 unsigned int timebase;
150 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
151 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
153 /* Initialize the Transmit and Receive Pointer */
154 writel((unsigned int)pDesc->rx_cmd_pt,
155 ATMEL_BASE_SPI0 + AT91_SPI_RPR);
156 writel((unsigned int)pDesc->tx_cmd_pt,
157 ATMEL_BASE_SPI0 + AT91_SPI_TPR);
159 /* Intialize the Transmit and Receive Counters */
160 writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
161 writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
163 if (pDesc->tx_data_size != 0) {
164 /* Initialize the Next Transmit and Next Receive Pointer */
165 writel((unsigned int)pDesc->rx_data_pt,
166 ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
167 writel((unsigned int)pDesc->tx_data_pt,
168 ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
170 /* Intialize the Next Transmit and Next Receive Counters */
171 writel(pDesc->rx_data_size,
172 ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
173 writel(pDesc->tx_data_size,
174 ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
177 /* arm simple, non interrupt dependent timer */
178 timebase = get_timer(0);
181 writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
182 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
183 while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
184 ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
186 writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
187 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
190 if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
191 printf("Error Timeout\n\r");
192 return DATAFLASH_ERROR;