2 * Copyright (C) 2007 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clk.h>
17 #include <asm/arch/hardware.h>
19 #include <asm/arch/at91_spi.h>
25 #include "atmel_spi.h"
27 DECLARE_GLOBAL_DATA_PTR;
31 static int spi_has_wdrbt(struct atmel_spi_slave *slave)
35 ver = spi_readl(slave, VERSION);
37 return (ATMEL_SPI_VERSION_REV(ver) >= 0x210);
45 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
46 unsigned int max_hz, unsigned int mode)
48 struct atmel_spi_slave *as;
53 if (!spi_cs_is_valid(bus, cs))
58 regs = (void *)ATMEL_BASE_SPI0;
60 #ifdef ATMEL_BASE_SPI1
62 regs = (void *)ATMEL_BASE_SPI1;
65 #ifdef ATMEL_BASE_SPI2
67 regs = (void *)ATMEL_BASE_SPI2;
70 #ifdef ATMEL_BASE_SPI3
72 regs = (void *)ATMEL_BASE_SPI3;
80 scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
81 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
82 /* Too low max SCK rate */
87 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
88 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
89 if (!(mode & SPI_CPHA))
90 csrx |= ATMEL_SPI_CSRx_NCPHA;
92 csrx |= ATMEL_SPI_CSRx_CPOL;
94 as = spi_alloc_slave(struct atmel_spi_slave, bus, cs);
99 as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
100 | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
101 if (spi_has_wdrbt(as))
102 as->mr |= ATMEL_SPI_MR_WDRBT;
104 spi_writel(as, CSR(cs), csrx);
109 void spi_free_slave(struct spi_slave *slave)
111 struct atmel_spi_slave *as = to_atmel_spi(slave);
116 int spi_claim_bus(struct spi_slave *slave)
118 struct atmel_spi_slave *as = to_atmel_spi(slave);
120 /* Enable the SPI hardware */
121 spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
124 * Select the slave. This should set SCK to the correct
125 * initial state, etc.
127 spi_writel(as, MR, as->mr);
132 void spi_release_bus(struct spi_slave *slave)
134 struct atmel_spi_slave *as = to_atmel_spi(slave);
136 /* Disable the SPI hardware */
137 spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
140 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
141 const void *dout, void *din, unsigned long flags)
143 struct atmel_spi_slave *as = to_atmel_spi(slave);
148 const u8 *txp = dout;
153 /* Finish any previously submitted transfers */
157 * TODO: The controller can do non-multiple-of-8 bit
158 * transfers, but this driver currently doesn't support it.
160 * It's also not clear how such transfers are supposed to be
161 * represented as a stream of bytes...this is a limitation of
162 * the current SPI interface.
165 /* Errors always terminate an ongoing transfer */
166 flags |= SPI_XFER_END;
173 * The controller can do automatic CS control, but it is
174 * somewhat quirky, and it doesn't really buy us much anyway
175 * in the context of U-Boot.
177 if (flags & SPI_XFER_BEGIN) {
178 spi_cs_activate(slave);
180 * sometimes the RDR is not empty when we get here,
181 * in theory that should not happen, but it DOES happen.
182 * Read it here to be on the safe side.
183 * That also clears the OVRES flag. Required if the
184 * following loop exits due to OVRES!
189 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
190 status = spi_readl(as, SR);
192 if (status & ATMEL_SPI_SR_OVRES)
195 if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
200 spi_writel(as, TDR, value);
203 if (status & ATMEL_SPI_SR_RDRF) {
204 value = spi_readl(as, RDR);
212 if (flags & SPI_XFER_END) {
214 * Wait until the transfer is completely done before
218 status = spi_readl(as, SR);
219 } while (!(status & ATMEL_SPI_SR_TXEMPTY));
221 spi_cs_deactivate(slave);
229 #define MAX_CS_COUNT 4
231 struct atmel_spi_platdata {
232 struct at91_spi *regs;
235 struct atmel_spi_priv {
236 unsigned int freq; /* Default frequency */
239 struct gpio_desc cs_gpios[MAX_CS_COUNT];
242 static int atmel_spi_claim_bus(struct udevice *dev)
244 struct udevice *bus = dev_get_parent(dev);
245 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
246 struct atmel_spi_priv *priv = dev_get_priv(bus);
247 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
248 struct at91_spi *reg_base = bus_plat->regs;
249 u32 cs = slave_plat->cs;
250 u32 freq = priv->freq;
251 u32 scbr, csrx, mode;
253 scbr = (priv->bus_clk_rate + freq - 1) / freq;
254 if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
260 csrx = ATMEL_SPI_CSRx_SCBR(scbr);
261 csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
263 if (!(priv->mode & SPI_CPHA))
264 csrx |= ATMEL_SPI_CSRx_NCPHA;
265 if (priv->mode & SPI_CPOL)
266 csrx |= ATMEL_SPI_CSRx_CPOL;
268 writel(csrx, ®_base->csr[cs]);
270 mode = ATMEL_SPI_MR_MSTR |
271 ATMEL_SPI_MR_MODFDIS |
273 ATMEL_SPI_MR_PCS(~(1 << cs));
275 writel(mode, ®_base->mr);
277 writel(ATMEL_SPI_CR_SPIEN, ®_base->cr);
282 static int atmel_spi_release_bus(struct udevice *dev)
284 struct udevice *bus = dev_get_parent(dev);
285 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
287 writel(ATMEL_SPI_CR_SPIDIS, &bus_plat->regs->cr);
292 static void atmel_spi_cs_activate(struct udevice *dev)
294 struct udevice *bus = dev_get_parent(dev);
295 struct atmel_spi_priv *priv = dev_get_priv(bus);
296 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
297 u32 cs = slave_plat->cs;
299 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
302 dm_gpio_set_value(&priv->cs_gpios[cs], 0);
305 static void atmel_spi_cs_deactivate(struct udevice *dev)
307 struct udevice *bus = dev_get_parent(dev);
308 struct atmel_spi_priv *priv = dev_get_priv(bus);
309 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
310 u32 cs = slave_plat->cs;
312 if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
315 dm_gpio_set_value(&priv->cs_gpios[cs], 1);
318 static int atmel_spi_xfer(struct udevice *dev, unsigned int bitlen,
319 const void *dout, void *din, unsigned long flags)
321 struct udevice *bus = dev_get_parent(dev);
322 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
323 struct at91_spi *reg_base = bus_plat->regs;
325 u32 len_tx, len_rx, len;
327 const u8 *txp = dout;
335 * The controller can do non-multiple-of-8 bit
336 * transfers, but this driver currently doesn't support it.
338 * It's also not clear how such transfers are supposed to be
339 * represented as a stream of bytes...this is a limitation of
340 * the current SPI interface.
343 /* Errors always terminate an ongoing transfer */
344 flags |= SPI_XFER_END;
351 * The controller can do automatic CS control, but it is
352 * somewhat quirky, and it doesn't really buy us much anyway
353 * in the context of U-Boot.
355 if (flags & SPI_XFER_BEGIN) {
356 atmel_spi_cs_activate(dev);
359 * sometimes the RDR is not empty when we get here,
360 * in theory that should not happen, but it DOES happen.
361 * Read it here to be on the safe side.
362 * That also clears the OVRES flag. Required if the
363 * following loop exits due to OVRES!
365 readl(®_base->rdr);
368 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
369 status = readl(®_base->sr);
371 if (status & ATMEL_SPI_SR_OVRES)
374 if ((len_tx < len) && (status & ATMEL_SPI_SR_TDRE)) {
379 writel(value, ®_base->tdr);
383 if (status & ATMEL_SPI_SR_RDRF) {
384 value = readl(®_base->rdr);
392 if (flags & SPI_XFER_END) {
394 * Wait until the transfer is completely done before
397 wait_for_bit(__func__, ®_base->sr,
398 ATMEL_SPI_SR_TXEMPTY, true, 1000, false);
400 atmel_spi_cs_deactivate(dev);
406 static int atmel_spi_set_speed(struct udevice *bus, uint speed)
408 struct atmel_spi_priv *priv = dev_get_priv(bus);
415 static int atmel_spi_set_mode(struct udevice *bus, uint mode)
417 struct atmel_spi_priv *priv = dev_get_priv(bus);
424 static const struct dm_spi_ops atmel_spi_ops = {
425 .claim_bus = atmel_spi_claim_bus,
426 .release_bus = atmel_spi_release_bus,
427 .xfer = atmel_spi_xfer,
428 .set_speed = atmel_spi_set_speed,
429 .set_mode = atmel_spi_set_mode,
431 * cs_info is not needed, since we require all chip selects to be
432 * in the device tree explicitly
436 static int atmel_spi_enable_clk(struct udevice *bus)
438 struct atmel_spi_priv *priv = dev_get_priv(bus);
443 ret = clk_get_by_index(bus, 0, &clk);
447 ret = clk_enable(&clk);
451 clk_rate = clk_get_rate(&clk);
455 priv->bus_clk_rate = clk_rate;
462 static int atmel_spi_probe(struct udevice *bus)
464 struct atmel_spi_platdata *bus_plat = dev_get_platdata(bus);
465 struct atmel_spi_priv *priv = dev_get_priv(bus);
468 ret = atmel_spi_enable_clk(bus);
472 bus_plat->regs = (struct at91_spi *)devfdt_get_addr(bus);
474 ret = gpio_request_list_by_name(bus, "cs-gpios", priv->cs_gpios,
475 ARRAY_SIZE(priv->cs_gpios), 0);
477 pr_err("Can't get %s gpios! Error: %d", bus->name, ret);
481 for(i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
482 if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
485 dm_gpio_set_dir_flags(&priv->cs_gpios[i],
486 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
489 writel(ATMEL_SPI_CR_SWRST, &bus_plat->regs->cr);
494 static const struct udevice_id atmel_spi_ids[] = {
495 { .compatible = "atmel,at91rm9200-spi" },
499 U_BOOT_DRIVER(atmel_spi) = {
502 .of_match = atmel_spi_ids,
503 .ops = &atmel_spi_ops,
504 .platdata_auto_alloc_size = sizeof(struct atmel_spi_platdata),
505 .priv_auto_alloc_size = sizeof(struct atmel_spi_priv),
506 .probe = atmel_spi_probe,