2 * Driver for Blackfin On-Chip SPI device
4 * Copyright (c) 2005-2010 Analog Devices Inc.
6 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/blackfin.h>
16 #include <asm/clock.h>
18 #include <asm/portmux.h>
19 #include <asm/mach-common/bits/spi.h>
21 struct bfin_spi_slave {
22 struct spi_slave slave;
27 #define MAKE_SPI_FUNC(mmr, off) \
28 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
29 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
30 MAKE_SPI_FUNC(SPI_CTL, 0x00)
31 MAKE_SPI_FUNC(SPI_FLG, 0x04)
32 MAKE_SPI_FUNC(SPI_STAT, 0x08)
33 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
34 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
35 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
37 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
39 #define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
40 #ifdef CONFIG_BFIN_SPI_GPIO_CS
41 # define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
43 # define is_gpio_cs(cs) 0
46 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
49 return gpio_is_valid(gpio_cs(cs));
51 return (cs >= 1 && cs <= MAX_CTRL_CS);
54 void spi_cs_activate(struct spi_slave *slave)
56 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
58 if (is_gpio_cs(slave->cs)) {
59 unsigned int cs = gpio_cs(slave->cs);
60 gpio_set_value(cs, bss->flg);
61 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
65 ~((!bss->flg << 8) << slave->cs)) |
67 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
73 void spi_cs_deactivate(struct spi_slave *slave)
75 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
77 if (is_gpio_cs(slave->cs)) {
78 unsigned int cs = gpio_cs(slave->cs);
79 gpio_set_value(cs, !bss->flg);
80 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
84 /* make sure we force the cs to deassert rather than let the
85 * pin float back up. otherwise, exact timings may not be
86 * met some of the time leading to random behavior (ugh).
88 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
89 write_SPI_FLG(bss, flg);
91 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
93 flg &= ~(1 << slave->cs);
94 write_SPI_FLG(bss, flg);
95 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
106 # define SPI0_CTL SPI_CTL
109 #define SPI_PINS(n) \
110 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
111 static unsigned short pins[][5] = {
123 #define SPI_CS_PINS(n) \
125 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
126 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
129 static const unsigned short cs_pins[][7] = {
141 void spi_set_speed(struct spi_slave *slave, uint hz)
143 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
148 /* baud should be rounded up */
149 baud = DIV_ROUND_UP(clk, 2 * hz);
152 else if (baud > (u16)-1)
157 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
158 unsigned int max_hz, unsigned int mode)
160 struct bfin_spi_slave *bss;
163 if (!spi_cs_is_valid(bus, cs))
169 mmr_base = SPI0_CTL; break;
173 mmr_base = SPI1_CTL; break;
177 mmr_base = SPI2_CTL; break;
180 debug("%s: invalid bus %u\n", __func__, bus);
184 bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs);
188 bss->mmr_base = (void *)mmr_base;
189 bss->ctl = SPE | MSTR | TDBR_CORE;
190 if (mode & SPI_CPHA) bss->ctl |= CPHA;
191 if (mode & SPI_CPOL) bss->ctl |= CPOL;
192 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
193 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
194 spi_set_speed(&bss->slave, max_hz);
196 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
197 bus, cs, mmr_base, bss->ctl, bss->baud, bss->flg);
202 void spi_free_slave(struct spi_slave *slave)
204 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
208 int spi_claim_bus(struct spi_slave *slave)
210 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
212 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
214 if (is_gpio_cs(slave->cs)) {
215 unsigned int cs = gpio_cs(slave->cs);
216 gpio_request(cs, "bfin-spi");
217 gpio_direction_output(cs, !bss->flg);
218 pins[slave->bus][0] = P_DONTCARE;
220 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
221 peripheral_request_list(pins[slave->bus], "bfin-spi");
223 write_SPI_CTL(bss, bss->ctl);
224 write_SPI_BAUD(bss, bss->baud);
230 void spi_release_bus(struct spi_slave *slave)
232 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
234 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
236 peripheral_free_list(pins[slave->bus]);
237 if (is_gpio_cs(slave->cs))
238 gpio_free(gpio_cs(slave->cs));
240 write_SPI_CTL(bss, 0);
244 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
245 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
248 static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
251 /* discard invalid data and clear RXS */
253 /* todo: take advantage of hardware fifos */
255 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
256 debug("%s: tx:%x ", __func__, value);
257 write_SPI_TDBR(bss, value);
259 while ((read_SPI_STAT(bss) & TXS))
262 while (!(read_SPI_STAT(bss) & SPIF))
265 while (!(read_SPI_STAT(bss) & RXS))
268 value = read_SPI_RDBR(bss);
271 debug("rx:%x\n", value);
277 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
278 void *din, unsigned long flags)
280 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
283 uint bytes = bitlen / 8;
286 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
287 slave->bus, slave->cs, bitlen, bytes, flags);
292 /* we can only do 8 bit transfers */
294 flags |= SPI_XFER_END;
298 if (flags & SPI_XFER_BEGIN)
299 spi_cs_activate(slave);
301 ret = spi_pio_xfer(bss, tx, rx, bytes);
304 if (flags & SPI_XFER_END)
305 spi_cs_deactivate(slave);