2 * Driver for Blackfin On-Chip SPI device
4 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
15 #include <asm/blackfin.h>
17 #include <asm/portmux.h>
18 #include <asm/mach-common/bits/spi.h>
20 struct bfin_spi_slave {
21 struct spi_slave slave;
26 #define MAKE_SPI_FUNC(mmr, off) \
27 static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
28 static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
29 MAKE_SPI_FUNC(SPI_CTL, 0x00)
30 MAKE_SPI_FUNC(SPI_FLG, 0x04)
31 MAKE_SPI_FUNC(SPI_STAT, 0x08)
32 MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
33 MAKE_SPI_FUNC(SPI_RDBR, 0x10)
34 MAKE_SPI_FUNC(SPI_BAUD, 0x14)
36 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
40 #define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
41 #ifdef CONFIG_BFIN_SPI_GPIO_CS
42 # define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
44 # define is_gpio_cs(cs) 0
47 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
50 return gpio_is_valid(gpio_cs(cs));
52 return (cs >= 1 && cs <= MAX_CTRL_CS);
55 void spi_cs_activate(struct spi_slave *slave)
57 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
59 if (is_gpio_cs(slave->cs)) {
60 unsigned int cs = gpio_cs(slave->cs);
61 gpio_set_value(cs, bss->flg);
62 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
66 ~((!bss->flg << 8) << slave->cs)) |
68 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
74 void spi_cs_deactivate(struct spi_slave *slave)
76 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
78 if (is_gpio_cs(slave->cs)) {
79 unsigned int cs = gpio_cs(slave->cs);
80 gpio_set_value(cs, !bss->flg);
81 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
85 /* make sure we force the cs to deassert rather than let the
86 * pin float back up. otherwise, exact timings may not be
87 * met some of the time leading to random behavior (ugh).
89 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
90 write_SPI_FLG(bss, flg);
92 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
94 flg &= ~(1 << slave->cs);
95 write_SPI_FLG(bss, flg);
96 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
107 # define SPI0_CTL SPI_CTL
110 #define SPI_PINS(n) \
111 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
112 static unsigned short pins[][5] = {
124 #define SPI_CS_PINS(n) \
126 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
127 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
130 static const unsigned short cs_pins[][7] = {
142 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
143 unsigned int max_hz, unsigned int mode)
145 struct bfin_spi_slave *bss;
150 if (!spi_cs_is_valid(bus, cs))
153 if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
154 debug("%s: invalid bus %u\n", __func__, bus);
159 case 0: mmr_base = SPI0_CTL; break;
162 case 1: mmr_base = SPI1_CTL; break;
165 case 2: mmr_base = SPI2_CTL; break;
167 default: return NULL;
171 baud = sclk / (2 * max_hz);
172 /* baud should be rounded up */
173 if (sclk % (2 * max_hz))
177 else if (baud > (u16)-1)
180 bss = malloc(sizeof(*bss));
184 bss->slave.bus = bus;
186 bss->mmr_base = (void *)mmr_base;
187 bss->ctl = SPE | MSTR | TDBR_CORE;
188 if (mode & SPI_CPHA) bss->ctl |= CPHA;
189 if (mode & SPI_CPOL) bss->ctl |= CPOL;
190 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
192 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
194 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
195 bus, cs, mmr_base, bss->ctl, baud, bss->flg);
200 void spi_free_slave(struct spi_slave *slave)
202 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
206 int spi_claim_bus(struct spi_slave *slave)
208 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
210 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
212 if (is_gpio_cs(slave->cs)) {
213 unsigned int cs = gpio_cs(slave->cs);
214 gpio_request(cs, "bfin-spi");
215 gpio_direction_output(cs, !bss->flg);
216 pins[slave->bus][0] = P_DONTCARE;
218 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
219 peripheral_request_list(pins[slave->bus], "bfin-spi");
221 write_SPI_CTL(bss, bss->ctl);
222 write_SPI_BAUD(bss, bss->baud);
228 void spi_release_bus(struct spi_slave *slave)
230 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
232 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
234 peripheral_free_list(pins[slave->bus]);
235 if (is_gpio_cs(slave->cs))
236 gpio_free(gpio_cs(slave->cs));
238 write_SPI_CTL(bss, 0);
242 #ifndef CONFIG_BFIN_SPI_IDLE_VAL
243 # define CONFIG_BFIN_SPI_IDLE_VAL 0xff
246 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
247 void *din, unsigned long flags)
249 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
252 uint bytes = bitlen / 8;
255 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
256 slave->bus, slave->cs, bitlen, bytes, flags);
261 /* we can only do 8 bit transfers */
263 flags |= SPI_XFER_END;
267 if (flags & SPI_XFER_BEGIN)
268 spi_cs_activate(slave);
270 /* todo: take advantage of hardware fifos and setup RX dma */
272 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
273 debug("%s: tx:%x ", __func__, value);
274 write_SPI_TDBR(bss, value);
276 while ((read_SPI_STAT(bss) & TXS))
281 while (!(read_SPI_STAT(bss) & SPIF))
286 while (!(read_SPI_STAT(bss) & RXS))
291 value = read_SPI_RDBR(bss);
294 debug("rx:%x\n", value);
298 if (flags & SPI_XFER_END)
299 spi_cs_deactivate(slave);