3 * Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
14 #include "cadence_qspi.h"
16 #define CQSPI_STIG_READ 0
17 #define CQSPI_STIG_WRITE 1
18 #define CQSPI_INDIRECT_READ 2
19 #define CQSPI_INDIRECT_WRITE 3
21 DECLARE_GLOBAL_DATA_PTR;
23 static int cadence_spi_write_speed(struct udevice *bus, uint hz)
25 struct cadence_spi_platdata *plat = bus->platdata;
26 struct cadence_spi_priv *priv = dev_get_priv(bus);
28 cadence_qspi_apb_config_baudrate_div(priv->regbase,
29 CONFIG_CQSPI_REF_CLK, hz);
31 /* Reconfigure delay timing if speed is changed. */
32 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
33 plat->tshsl_ns, plat->tsd2d_ns,
34 plat->tchsh_ns, plat->tslch_ns);
39 /* Calibration sequence to determine the read data capture delay register */
40 static int spi_calibration(struct udevice *bus)
42 struct cadence_spi_platdata *plat = bus->platdata;
43 struct cadence_spi_priv *priv = dev_get_priv(bus);
44 void *base = priv->regbase;
45 u8 opcode_rdid = 0x9F;
46 unsigned int idcode = 0, temp = 0;
47 int err = 0, i, range_lo = -1, range_hi = -1;
49 /* start with slowest clock (1 MHz) */
50 cadence_spi_write_speed(bus, 1000000);
52 /* configure the read data capture delay register to 0 */
53 cadence_qspi_apb_readdata_capture(base, 1, 0);
56 cadence_qspi_apb_controller_enable(base);
58 /* read the ID which will be our golden value */
59 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
62 puts("SF: Calibration failed (read)\n");
66 /* use back the intended clock and find low range */
67 cadence_spi_write_speed(bus, plat->max_hz);
68 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
70 cadence_qspi_apb_controller_disable(base);
72 /* reconfigure the read data capture delay register */
73 cadence_qspi_apb_readdata_capture(base, 1, i);
75 /* Enable back QSPI */
76 cadence_qspi_apb_controller_enable(base);
78 /* issue a RDID to get the ID value */
79 err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
82 puts("SF: Calibration failed (read)\n");
86 /* search for range lo */
87 if (range_lo == -1 && temp == idcode) {
92 /* search for range hi */
93 if (range_lo != -1 && temp != idcode) {
100 if (range_lo == -1) {
101 puts("SF: Calibration failed (low range)\n");
105 /* Disable QSPI for subsequent initialization */
106 cadence_qspi_apb_controller_disable(base);
108 /* configure the final value for read data capture delay register */
109 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
110 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
111 (range_hi + range_lo) / 2, range_lo, range_hi);
113 /* just to ensure we do once only when speed or chip select change */
114 priv->qspi_calibrated_hz = plat->max_hz;
115 priv->qspi_calibrated_cs = spi_chip_select(bus);
120 static int cadence_spi_set_speed(struct udevice *bus, uint hz)
122 struct cadence_spi_platdata *plat = bus->platdata;
123 struct cadence_spi_priv *priv = dev_get_priv(bus);
127 cadence_qspi_apb_controller_disable(priv->regbase);
129 cadence_spi_write_speed(bus, hz);
131 /* Calibration required for different SCLK speed or chip select */
132 if (priv->qspi_calibrated_hz != plat->max_hz ||
133 priv->qspi_calibrated_cs != spi_chip_select(bus)) {
134 err = spi_calibration(bus);
140 cadence_qspi_apb_controller_enable(priv->regbase);
142 debug("%s: speed=%d\n", __func__, hz);
147 static int cadence_spi_probe(struct udevice *bus)
149 struct cadence_spi_platdata *plat = bus->platdata;
150 struct cadence_spi_priv *priv = dev_get_priv(bus);
152 priv->regbase = plat->regbase;
153 priv->ahbbase = plat->ahbbase;
155 if (!priv->qspi_is_init) {
156 cadence_qspi_apb_controller_init(plat);
157 priv->qspi_is_init = 1;
163 static int cadence_spi_set_mode(struct udevice *bus, uint mode)
165 struct cadence_spi_priv *priv = dev_get_priv(bus);
166 unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
167 unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
170 cadence_qspi_apb_controller_disable(priv->regbase);
173 cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
176 cadence_qspi_apb_controller_enable(priv->regbase);
181 static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
182 const void *dout, void *din, unsigned long flags)
184 struct udevice *bus = dev->parent;
185 struct cadence_spi_platdata *plat = bus->platdata;
186 struct cadence_spi_priv *priv = dev_get_priv(bus);
187 void *base = priv->regbase;
188 u8 *cmd_buf = priv->cmd_buf;
191 u32 mode = CQSPI_STIG_WRITE;
193 if (flags & SPI_XFER_BEGIN) {
194 /* copy command to local buffer */
195 priv->cmd_len = bitlen / 8;
196 memcpy(cmd_buf, dout, priv->cmd_len);
199 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
200 /* if start and end bit are set, the data bytes is 0. */
203 data_bytes = bitlen / 8;
205 debug("%s: len=%d [bytes]\n", __func__, data_bytes);
207 /* Set Chip select */
208 cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
209 CONFIG_CQSPI_DECODER);
211 if ((flags & SPI_XFER_END) || (flags == 0)) {
212 if (priv->cmd_len == 0) {
213 printf("QSPI: Error, command is empty.\n");
217 if (din && data_bytes) {
219 /* Use STIG if no address. */
220 if (!CQSPI_IS_ADDR(priv->cmd_len))
221 mode = CQSPI_STIG_READ;
223 mode = CQSPI_INDIRECT_READ;
224 } else if (dout && !(flags & SPI_XFER_BEGIN)) {
226 if (!CQSPI_IS_ADDR(priv->cmd_len))
227 mode = CQSPI_STIG_WRITE;
229 mode = CQSPI_INDIRECT_WRITE;
233 case CQSPI_STIG_READ:
234 err = cadence_qspi_apb_command_read(
235 base, priv->cmd_len, cmd_buf,
239 case CQSPI_STIG_WRITE:
240 err = cadence_qspi_apb_command_write(base,
241 priv->cmd_len, cmd_buf,
244 case CQSPI_INDIRECT_READ:
245 err = cadence_qspi_apb_indirect_read_setup(plat,
246 priv->cmd_len, cmd_buf);
248 err = cadence_qspi_apb_indirect_read_execute
249 (plat, data_bytes, din);
252 case CQSPI_INDIRECT_WRITE:
253 err = cadence_qspi_apb_indirect_write_setup
254 (plat, priv->cmd_len, cmd_buf);
256 err = cadence_qspi_apb_indirect_write_execute
257 (plat, data_bytes, dout);
265 if (flags & SPI_XFER_END) {
266 /* clear command buffer */
267 memset(cmd_buf, 0, sizeof(priv->cmd_buf));
275 static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
277 struct cadence_spi_platdata *plat = bus->platdata;
278 const void *blob = gd->fdt_blob;
279 int node = bus->of_offset;
284 /* 2 base addresses are needed, lets get them from the DT */
285 ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
287 printf("Error: Can't get base addresses (ret=%d)!\n", ret);
291 plat->regbase = (void *)data[0];
292 plat->ahbbase = (void *)data[2];
294 /* Use 500KHz as a suitable default */
295 plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
298 /* All other paramters are embedded in the child node */
299 subnode = fdt_first_subnode(blob, node);
301 printf("Error: subnode with SPI flash config missing!\n");
305 /* Read other parameters from DT */
306 plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
307 plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
308 plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
309 plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
310 plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
311 plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
312 plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128);
314 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
315 __func__, plat->regbase, plat->ahbbase, plat->max_hz,
321 static const struct dm_spi_ops cadence_spi_ops = {
322 .xfer = cadence_spi_xfer,
323 .set_speed = cadence_spi_set_speed,
324 .set_mode = cadence_spi_set_mode,
326 * cs_info is not needed, since we require all chip selects to be
327 * in the device tree explicitly
331 static const struct udevice_id cadence_spi_ids[] = {
332 { .compatible = "cadence,qspi" },
336 U_BOOT_DRIVER(cadence_spi) = {
337 .name = "cadence_spi",
339 .of_match = cadence_spi_ids,
340 .ops = &cadence_spi_ops,
341 .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
342 .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
343 .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
344 .probe = cadence_spi_probe,