2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <asm/errno.h>
31 #include "cadence_qspi.h"
33 #define CQSPI_REG_POLL_US (1) /* 1us */
34 #define CQSPI_REG_RETRY (10000)
35 #define CQSPI_POLL_IDLE_RETRY (3)
37 #define CQSPI_FIFO_WIDTH (4)
39 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
42 #define CQSPI_INST_TYPE_SINGLE (0)
43 #define CQSPI_INST_TYPE_DUAL (1)
44 #define CQSPI_INST_TYPE_QUAD (2)
46 #define CQSPI_STIG_DATA_LEN_MAX (8)
47 #define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
49 #define CQSPI_DUMMY_CLKS_PER_BYTE (8)
50 #define CQSPI_DUMMY_BYTES_MAX (4)
53 #define CQSPI_REG_SRAM_FILL_THRESHOLD \
54 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
55 /****************************************************************************
56 * Controller's configuration and status register (offset from QSPI_BASE)
57 ****************************************************************************/
58 #define CQSPI_REG_CONFIG 0x00
59 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1
60 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
61 #define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
62 #define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
63 #define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
64 #define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
65 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
66 #define CQSPI_REG_CONFIG_BAUD_LSB 19
67 #define CQSPI_REG_CONFIG_IDLE_LSB 31
68 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
69 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
71 #define CQSPI_REG_RD_INSTR 0x04
72 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
76 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
77 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
78 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
79 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
80 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
81 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
83 #define CQSPI_REG_WR_INSTR 0x08
84 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
86 #define CQSPI_REG_DELAY 0x0C
87 #define CQSPI_REG_DELAY_TSLCH_LSB 0
88 #define CQSPI_REG_DELAY_TCHSH_LSB 8
89 #define CQSPI_REG_DELAY_TSD2D_LSB 16
90 #define CQSPI_REG_DELAY_TSHSL_LSB 24
91 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
92 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
93 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
94 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
96 #define CQSPI_READLCAPTURE 0x10
97 #define CQSPI_READLCAPTURE_BYPASS_LSB 0
98 #define CQSPI_READLCAPTURE_DELAY_LSB 1
99 #define CQSPI_READLCAPTURE_DELAY_MASK 0xF
101 #define CQSPI_REG_SIZE 0x14
102 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
103 #define CQSPI_REG_SIZE_PAGE_LSB 4
104 #define CQSPI_REG_SIZE_BLOCK_LSB 16
105 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
106 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
107 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
109 #define CQSPI_REG_SRAMPARTITION 0x18
110 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
112 #define CQSPI_REG_REMAP 0x24
113 #define CQSPI_REG_MODE_BIT 0x28
115 #define CQSPI_REG_SDRAMLEVEL 0x2C
116 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
117 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
118 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
119 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
121 #define CQSPI_REG_IRQSTATUS 0x40
122 #define CQSPI_REG_IRQMASK 0x44
124 #define CQSPI_REG_INDIRECTRD 0x60
125 #define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
126 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
127 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
128 #define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
130 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
131 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
132 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
134 #define CQSPI_REG_CMDCTRL 0x90
135 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
136 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
137 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
138 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
139 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
140 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
141 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
142 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
143 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
144 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
145 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
146 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
147 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
148 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
149 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
151 #define CQSPI_REG_INDIRECTWR 0x70
152 #define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
153 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
154 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
155 #define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
157 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
158 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
159 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
161 #define CQSPI_REG_CMDADDRESS 0x94
162 #define CQSPI_REG_CMDREADDATALOWER 0xA0
163 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
164 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
165 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
167 #define CQSPI_REG_IS_IDLE(base) \
168 ((readl(base + CQSPI_REG_CONFIG) >> \
169 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
171 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
172 ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
174 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
175 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
176 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
178 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
179 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
180 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
182 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
183 unsigned int addr_width)
187 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
190 addr = (addr << 8) | addr_buf[3];
195 static void cadence_qspi_apb_read_fifo_data(void *dest,
196 const void *src_ahb_addr, unsigned int bytes)
199 int remaining = bytes;
200 unsigned int *dest_ptr = (unsigned int *)dest;
201 unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
203 while (remaining >= sizeof(dest_ptr)) {
204 *dest_ptr = readl(src_ptr);
205 remaining -= sizeof(src_ptr);
210 temp = readl(src_ptr);
211 memcpy(dest_ptr, &temp, remaining);
217 static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
218 const void *src, unsigned int bytes)
220 unsigned int temp = 0;
222 int remaining = bytes;
223 unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
224 unsigned int *src_ptr = (unsigned int *)src;
226 while (remaining >= CQSPI_FIFO_WIDTH) {
227 for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
228 writel(*(src_ptr+i), dest_ptr+i);
229 src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
230 remaining -= CQSPI_FIFO_WIDTH;
234 i = remaining/sizeof(dest_ptr);
235 memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
236 writel(temp, dest_ptr+i);
237 for (--i; i >= 0; i--)
238 writel(*(src_ptr+i), dest_ptr+i);
243 /* Read from SRAM FIFO with polling SRAM fill level. */
244 static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
245 const void *src_addr, unsigned int num_bytes)
247 unsigned int remaining = num_bytes;
249 unsigned int sram_level = 0;
250 unsigned char *dest = (unsigned char *)dest_addr;
252 while (remaining > 0) {
253 retry = CQSPI_REG_RETRY;
255 sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
262 printf("QSPI: No receive data after polling for %d times\n",
267 sram_level *= CQSPI_FIFO_WIDTH;
268 sram_level = sram_level > remaining ? remaining : sram_level;
270 /* Read data from FIFO. */
271 cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
273 remaining -= sram_level;
279 /* Write to SRAM FIFO with polling SRAM fill level. */
280 static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
281 const void *src_addr, unsigned int num_bytes)
283 const void *reg_base = plat->regbase;
284 void *dest_addr = plat->ahbbase;
285 unsigned int retry = CQSPI_REG_RETRY;
286 unsigned int sram_level;
287 unsigned int wr_bytes;
288 unsigned char *src = (unsigned char *)src_addr;
289 int remaining = num_bytes;
290 unsigned int page_size = plat->page_size;
291 unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
293 while (remaining > 0) {
294 retry = CQSPI_REG_RETRY;
296 sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
297 if (sram_level <= sram_threshold_words)
301 printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
302 sram_level, sram_threshold_words);
305 /* Write a page or remaining bytes. */
306 wr_bytes = (remaining > page_size) ?
307 page_size : remaining;
309 cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
311 remaining -= wr_bytes;
317 void cadence_qspi_apb_controller_enable(void *reg_base)
320 reg = readl(reg_base + CQSPI_REG_CONFIG);
321 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
322 writel(reg, reg_base + CQSPI_REG_CONFIG);
326 void cadence_qspi_apb_controller_disable(void *reg_base)
329 reg = readl(reg_base + CQSPI_REG_CONFIG);
330 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
331 writel(reg, reg_base + CQSPI_REG_CONFIG);
335 /* Return 1 if idle, otherwise return 0 (busy). */
336 static unsigned int cadence_qspi_wait_idle(void *reg_base)
338 unsigned int start, count = 0;
339 /* timeout in unit of ms */
340 unsigned int timeout = 5000;
342 start = get_timer(0);
343 for ( ; get_timer(start) < timeout ; ) {
344 if (CQSPI_REG_IS_IDLE(reg_base))
349 * Ensure the QSPI controller is in true idle state after
350 * reading back the same idle status consecutively
352 if (count >= CQSPI_POLL_IDLE_RETRY)
356 /* Timeout, still in busy mode. */
357 printf("QSPI: QSPI is still busy after poll for %d times.\n",
362 void cadence_qspi_apb_readdata_capture(void *reg_base,
363 unsigned int bypass, unsigned int delay)
366 cadence_qspi_apb_controller_disable(reg_base);
368 reg = readl(reg_base + CQSPI_READLCAPTURE);
371 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
373 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
375 reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
376 << CQSPI_READLCAPTURE_DELAY_LSB);
378 reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
379 << CQSPI_READLCAPTURE_DELAY_LSB);
381 writel(reg, reg_base + CQSPI_READLCAPTURE);
383 cadence_qspi_apb_controller_enable(reg_base);
387 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
388 unsigned int ref_clk_hz, unsigned int sclk_hz)
393 cadence_qspi_apb_controller_disable(reg_base);
394 reg = readl(reg_base + CQSPI_REG_CONFIG);
395 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
397 div = ref_clk_hz / sclk_hz;
402 /* Check if even number. */
406 if (ref_clk_hz % sclk_hz)
407 /* ensure generated SCLK doesn't exceed user
414 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
415 ref_clk_hz, sclk_hz, div);
417 div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
419 writel(reg, reg_base + CQSPI_REG_CONFIG);
421 cadence_qspi_apb_controller_enable(reg_base);
425 void cadence_qspi_apb_set_clk_mode(void *reg_base,
426 unsigned int clk_pol, unsigned int clk_pha)
430 cadence_qspi_apb_controller_disable(reg_base);
431 reg = readl(reg_base + CQSPI_REG_CONFIG);
433 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
435 reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
436 reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
438 writel(reg, reg_base + CQSPI_REG_CONFIG);
440 cadence_qspi_apb_controller_enable(reg_base);
444 void cadence_qspi_apb_chipselect(void *reg_base,
445 unsigned int chip_select, unsigned int decoder_enable)
449 cadence_qspi_apb_controller_disable(reg_base);
451 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
454 reg = readl(reg_base + CQSPI_REG_CONFIG);
456 if (decoder_enable) {
457 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
459 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
460 /* Convert CS if without decoder.
466 chip_select = 0xF & ~(1 << chip_select);
469 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
470 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
471 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
472 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
473 writel(reg, reg_base + CQSPI_REG_CONFIG);
475 cadence_qspi_apb_controller_enable(reg_base);
479 void cadence_qspi_apb_delay(void *reg_base,
480 unsigned int ref_clk, unsigned int sclk_hz,
481 unsigned int tshsl_ns, unsigned int tsd2d_ns,
482 unsigned int tchsh_ns, unsigned int tslch_ns)
484 unsigned int ref_clk_ns;
485 unsigned int sclk_ns;
486 unsigned int tshsl, tchsh, tslch, tsd2d;
489 cadence_qspi_apb_controller_disable(reg_base);
492 ref_clk_ns = (1000000000) / ref_clk;
495 sclk_ns = (1000000000) / sclk_hz;
497 /* Plus 1 to round up 1 clock cycle. */
498 tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
499 tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
500 tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
501 tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
503 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
504 << CQSPI_REG_DELAY_TSHSL_LSB);
505 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
506 << CQSPI_REG_DELAY_TCHSH_LSB);
507 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
508 << CQSPI_REG_DELAY_TSLCH_LSB);
509 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
510 << CQSPI_REG_DELAY_TSD2D_LSB);
511 writel(reg, reg_base + CQSPI_REG_DELAY);
513 cadence_qspi_apb_controller_enable(reg_base);
517 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
521 cadence_qspi_apb_controller_disable(plat->regbase);
523 /* Configure the device size and address bytes */
524 reg = readl(plat->regbase + CQSPI_REG_SIZE);
525 /* Clear the previous value */
526 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
527 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
528 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
529 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
530 writel(reg, plat->regbase + CQSPI_REG_SIZE);
532 /* Configure the remap address register, no remap */
533 writel(0, plat->regbase + CQSPI_REG_REMAP);
535 /* Indirect mode configurations */
536 writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
538 /* Disable all interrupts */
539 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
541 cadence_qspi_apb_controller_enable(plat->regbase);
545 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
548 unsigned int retry = CQSPI_REG_RETRY;
550 /* Write the CMDCTRL without start execution. */
551 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
553 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
554 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
557 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
558 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
564 printf("QSPI: flash command execution timeout\n");
568 /* Polling QSPI idle status. */
569 if (!cadence_qspi_wait_idle(reg_base))
575 /* For command RDID, RDSR. */
576 int cadence_qspi_apb_command_read(void *reg_base,
577 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
581 unsigned int read_len;
584 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
585 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
590 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
592 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
594 /* 0 means 1 byte. */
595 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
596 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
597 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
601 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
603 /* Put the read value into rx_buf */
604 read_len = (rxlen > 4) ? 4 : rxlen;
605 memcpy(rxbuf, ®, read_len);
609 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
611 read_len = rxlen - read_len;
612 memcpy(rxbuf, ®, read_len);
617 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
618 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
619 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
621 unsigned int reg = 0;
622 unsigned int addr_value;
623 unsigned int wr_data;
626 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
627 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
632 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
634 if (cmdlen == 4 || cmdlen == 5) {
635 /* Command with address */
636 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
637 /* Number of bytes to write. */
638 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
639 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
641 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
642 cmdlen >= 5 ? 4 : 3);
644 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
648 /* writing data = yes */
649 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
650 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
651 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
653 wr_len = txlen > 4 ? 4 : txlen;
654 memcpy(&wr_data, txbuf, wr_len);
655 writel(wr_data, reg_base +
656 CQSPI_REG_CMDWRITEDATALOWER);
660 wr_len = txlen - wr_len;
661 memcpy(&wr_data, txbuf, wr_len);
662 writel(wr_data, reg_base +
663 CQSPI_REG_CMDWRITEDATAUPPER);
667 /* Execute the command */
668 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
671 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
672 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
673 unsigned int cmdlen, const u8 *cmdbuf)
677 unsigned int addr_value;
678 unsigned int dummy_clk;
679 unsigned int dummy_bytes;
680 unsigned int addr_bytes;
683 * Identify addr_byte. All NOR flash device drivers are using fast read
684 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
685 * With that, the length is in value of 5 or 6. Only FRAM chip from
686 * ramtron using normal read (which won't need dummy byte).
687 * Unlikely NOR flash using normal read due to performance issue.
690 /* to cater fast read where cmd + addr + dummy */
691 addr_bytes = cmdlen - 2;
693 /* for normal read (only ramtron as of now) */
694 addr_bytes = cmdlen - 1;
696 /* Setup the indirect trigger address */
697 writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
698 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
700 /* Configure the opcode */
701 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
703 #if (CONFIG_SPI_FLASH_QUAD == 1)
704 /* Instruction and address at DQ0, data at DQ0-3. */
705 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
709 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
710 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
712 /* The remaining lenght is dummy bytes. */
713 dummy_bytes = cmdlen - addr_bytes - 1;
715 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
716 dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
718 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
719 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
720 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
722 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
725 /* Convert to clock cycles. */
726 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
727 /* Need to minus the mode byte (8 clocks). */
728 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
731 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
732 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
735 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
737 /* set device size */
738 reg = readl(plat->regbase + CQSPI_REG_SIZE);
739 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
740 reg |= (addr_bytes - 1);
741 writel(reg, plat->regbase + CQSPI_REG_SIZE);
745 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
746 unsigned int rxlen, u8 *rxbuf)
750 writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
752 /* Start the indirect read transfer */
753 writel(CQSPI_REG_INDIRECTRD_START_MASK,
754 plat->regbase + CQSPI_REG_INDIRECTRD);
756 if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
757 (const void *)plat->ahbbase, rxlen))
760 /* Check flash indirect controller */
761 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
762 if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
763 reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
764 printf("QSPI: indirect completion status error with reg 0x%08x\n",
769 /* Clear indirect completion status */
770 writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
771 plat->regbase + CQSPI_REG_INDIRECTRD);
775 /* Cancel the indirect read */
776 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
777 plat->regbase + CQSPI_REG_INDIRECTRD);
781 /* Opcode + Address (3/4 bytes) */
782 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
783 unsigned int cmdlen, const u8 *cmdbuf)
786 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
788 if (cmdlen < 4 || cmdbuf == NULL) {
789 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
790 cmdlen, (unsigned int)cmdbuf);
793 /* Setup the indirect trigger address */
794 writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
795 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
797 /* Configure the opcode */
798 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
799 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
801 /* Setup write address. */
802 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
803 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
805 reg = readl(plat->regbase + CQSPI_REG_SIZE);
806 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
807 reg |= (addr_bytes - 1);
808 writel(reg, plat->regbase + CQSPI_REG_SIZE);
812 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
813 unsigned int txlen, const u8 *txbuf)
815 unsigned int reg = 0;
818 /* Configure the indirect read transfer bytes */
819 writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
821 /* Start the indirect write transfer */
822 writel(CQSPI_REG_INDIRECTWR_START_MASK,
823 plat->regbase + CQSPI_REG_INDIRECTWR);
825 if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
828 /* Wait until last write is completed (FIFO empty) */
829 retry = CQSPI_REG_RETRY;
831 reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
839 printf("QSPI: timeout for indirect write\n");
843 /* Check flash indirect controller status */
844 retry = CQSPI_REG_RETRY;
846 reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
847 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
852 if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
853 printf("QSPI: indirect completion status error with reg 0x%08x\n",
858 /* Clear indirect completion status */
859 writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
860 plat->regbase + CQSPI_REG_INDIRECTWR);
864 /* Cancel the indirect write */
865 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
866 plat->regbase + CQSPI_REG_INDIRECTWR);
870 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
874 /* enter XiP mode immediately and enable direct mode */
875 reg = readl(reg_base + CQSPI_REG_CONFIG);
876 reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
877 reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
878 reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
879 writel(reg, reg_base + CQSPI_REG_CONFIG);
881 /* keep the XiP mode */
882 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
884 /* Enable mode bit at devrd */
885 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
886 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
887 writel(reg, reg_base + CQSPI_REG_RD_INSTR);