git.sur5r.net Git - u-boot/blob - drivers/spi/cadence_qspi_apb.c

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *  - Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  *  - Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *  - Neither the name of the Altera Corporation nor the
  13  *    names of its contributors may be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/errno.h>
  31 #include <wait_bit.h>
  32 #include <spi.h>
  33 #include "cadence_qspi.h"
  34
  35 #define CQSPI_REG_POLL_US                       (1) /* 1us */
  36 #define CQSPI_REG_RETRY                         (10000)
  37 #define CQSPI_POLL_IDLE_RETRY                   (3)
  38
  39 #define CQSPI_FIFO_WIDTH                        (4)
  40
  41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS          (50)
  42
  43 /* Transfer mode */
  44 #define CQSPI_INST_TYPE_SINGLE                  (0)
  45 #define CQSPI_INST_TYPE_DUAL                    (1)
  46 #define CQSPI_INST_TYPE_QUAD                    (2)
  47
  48 #define CQSPI_STIG_DATA_LEN_MAX                 (8)
  49
  50 #define CQSPI_DUMMY_CLKS_PER_BYTE               (8)
  51 #define CQSPI_DUMMY_BYTES_MAX                   (4)
  52
  53
  54 #define CQSPI_REG_SRAM_FILL_THRESHOLD   \
  55         ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
  56 /****************************************************************************
  57  * Controller's configuration and status register (offset from QSPI_BASE)
  58  ****************************************************************************/
  59 #define CQSPI_REG_CONFIG                        0x00
  60 #define CQSPI_REG_CONFIG_CLK_POL_LSB            1
  61 #define CQSPI_REG_CONFIG_CLK_PHA_LSB            2
  62 #define CQSPI_REG_CONFIG_ENABLE_MASK            BIT(0)
  63 #define CQSPI_REG_CONFIG_DIRECT_MASK            BIT(7)
  64 #define CQSPI_REG_CONFIG_DECODE_MASK            BIT(9)
  65 #define CQSPI_REG_CONFIG_XIP_IMM_MASK           BIT(18)
  66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB         10
  67 #define CQSPI_REG_CONFIG_BAUD_LSB               19
  68 #define CQSPI_REG_CONFIG_IDLE_LSB               31
  69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK        0xF
  70 #define CQSPI_REG_CONFIG_BAUD_MASK              0xF
  71
  72 #define CQSPI_REG_RD_INSTR                      0x04
  73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
  74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
  75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
  76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
  77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
  78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB            24
  79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK      0x3
  80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK       0x3
  81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK       0x3
  82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK           0x1F
  83
  84 #define CQSPI_REG_WR_INSTR                      0x08
  85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB           0
  86
  87 #define CQSPI_REG_DELAY                         0x0C
  88 #define CQSPI_REG_DELAY_TSLCH_LSB               0
  89 #define CQSPI_REG_DELAY_TCHSH_LSB               8
  90 #define CQSPI_REG_DELAY_TSD2D_LSB               16
  91 #define CQSPI_REG_DELAY_TSHSL_LSB               24
  92 #define CQSPI_REG_DELAY_TSLCH_MASK              0xFF
  93 #define CQSPI_REG_DELAY_TCHSH_MASK              0xFF
  94 #define CQSPI_REG_DELAY_TSD2D_MASK              0xFF
  95 #define CQSPI_REG_DELAY_TSHSL_MASK              0xFF
  96
  97 #define CQSPI_READLCAPTURE                      0x10
  98 #define CQSPI_READLCAPTURE_BYPASS_LSB           0
  99 #define CQSPI_READLCAPTURE_DELAY_LSB            1
 100 #define CQSPI_READLCAPTURE_DELAY_MASK           0xF
 101
 102 #define CQSPI_REG_SIZE                          0x14
 103 #define CQSPI_REG_SIZE_ADDRESS_LSB              0
 104 #define CQSPI_REG_SIZE_PAGE_LSB                 4
 105 #define CQSPI_REG_SIZE_BLOCK_LSB                16
 106 #define CQSPI_REG_SIZE_ADDRESS_MASK             0xF
 107 #define CQSPI_REG_SIZE_PAGE_MASK                0xFFF
 108 #define CQSPI_REG_SIZE_BLOCK_MASK               0x3F
 109
 110 #define CQSPI_REG_SRAMPARTITION                 0x18
 111 #define CQSPI_REG_INDIRECTTRIGGER               0x1C
 112
 113 #define CQSPI_REG_REMAP                         0x24
 114 #define CQSPI_REG_MODE_BIT                      0x28
 115
 116 #define CQSPI_REG_SDRAMLEVEL                    0x2C
 117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB             0
 118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB             16
 119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK            0xFFFF
 120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK            0xFFFF
 121
 122 #define CQSPI_REG_IRQSTATUS                     0x40
 123 #define CQSPI_REG_IRQMASK                       0x44
 124
 125 #define CQSPI_REG_INDIRECTRD                    0x60
 126 #define CQSPI_REG_INDIRECTRD_START_MASK         BIT(0)
 127 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK        BIT(1)
 128 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK    BIT(2)
 129 #define CQSPI_REG_INDIRECTRD_DONE_MASK          BIT(5)
 130
 131 #define CQSPI_REG_INDIRECTRDWATERMARK           0x64
 132 #define CQSPI_REG_INDIRECTRDSTARTADDR           0x68
 133 #define CQSPI_REG_INDIRECTRDBYTES               0x6C
 134
 135 #define CQSPI_REG_CMDCTRL                       0x90
 136 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK          BIT(0)
 137 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK       BIT(1)
 138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB             7
 139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB          12
 140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB             15
 141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB         16
 142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB           19
 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB          20
 144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB             23
 145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB            24
 146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK            0x1F
 147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK         0x7
 148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK        0x3
 149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK         0x7
 150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK           0xFF
 151
 152 #define CQSPI_REG_INDIRECTWR                    0x70
 153 #define CQSPI_REG_INDIRECTWR_START_MASK         BIT(0)
 154 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK        BIT(1)
 155 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK    BIT(2)
 156 #define CQSPI_REG_INDIRECTWR_DONE_MASK          BIT(5)
 157
 158 #define CQSPI_REG_INDIRECTWRWATERMARK           0x74
 159 #define CQSPI_REG_INDIRECTWRSTARTADDR           0x78
 160 #define CQSPI_REG_INDIRECTWRBYTES               0x7C
 161
 162 #define CQSPI_REG_CMDADDRESS                    0x94
 163 #define CQSPI_REG_CMDREADDATALOWER              0xA0
 164 #define CQSPI_REG_CMDREADDATAUPPER              0xA4
 165 #define CQSPI_REG_CMDWRITEDATALOWER             0xA8
 166 #define CQSPI_REG_CMDWRITEDATAUPPER             0xAC
 167
 168 #define CQSPI_REG_IS_IDLE(base)                                 \
 169         ((readl(base + CQSPI_REG_CONFIG) >>             \
 170                 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
 171
 172 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns)           \
 173         ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
 174
 175 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)                       \
 176         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 177         CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
 178
 179 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)                       \
 180         (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>   \
 181         CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
 182
 183 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
 184         unsigned int addr_width)
 185 {
 186         unsigned int addr;
 187
 188         addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
 189
 190         if (addr_width == 4)
 191                 addr = (addr << 8) | addr_buf[3];
 192
 193         return addr;
 194 }
 195
 196 void cadence_qspi_apb_controller_enable(void *reg_base)
 197 {
 198         unsigned int reg;
 199         reg = readl(reg_base + CQSPI_REG_CONFIG);
 200         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 201         writel(reg, reg_base + CQSPI_REG_CONFIG);
 202         return;
 203 }
 204
 205 void cadence_qspi_apb_controller_disable(void *reg_base)
 206 {
 207         unsigned int reg;
 208         reg = readl(reg_base + CQSPI_REG_CONFIG);
 209         reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
 210         writel(reg, reg_base + CQSPI_REG_CONFIG);
 211         return;
 212 }
 213
 214 /* Return 1 if idle, otherwise return 0 (busy). */
 215 static unsigned int cadence_qspi_wait_idle(void *reg_base)
 216 {
 217         unsigned int start, count = 0;
 218         /* timeout in unit of ms */
 219         unsigned int timeout = 5000;
 220
 221         start = get_timer(0);
 222         for ( ; get_timer(start) < timeout ; ) {
 223                 if (CQSPI_REG_IS_IDLE(reg_base))
 224                         count++;
 225                 else
 226                         count = 0;
 227                 /*
 228                  * Ensure the QSPI controller is in true idle state after
 229                  * reading back the same idle status consecutively
 230                  */
 231                 if (count >= CQSPI_POLL_IDLE_RETRY)
 232                         return 1;
 233         }
 234
 235         /* Timeout, still in busy mode. */
 236         printf("QSPI: QSPI is still busy after poll for %d times.\n",
 237                CQSPI_REG_RETRY);
 238         return 0;
 239 }
 240
 241 void cadence_qspi_apb_readdata_capture(void *reg_base,
 242                                 unsigned int bypass, unsigned int delay)
 243 {
 244         unsigned int reg;
 245         cadence_qspi_apb_controller_disable(reg_base);
 246
 247         reg = readl(reg_base + CQSPI_READLCAPTURE);
 248
 249         if (bypass)
 250                 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 251         else
 252                 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
 253
 254         reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
 255                 << CQSPI_READLCAPTURE_DELAY_LSB);
 256
 257         reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
 258                 << CQSPI_READLCAPTURE_DELAY_LSB);
 259
 260         writel(reg, reg_base + CQSPI_READLCAPTURE);
 261
 262         cadence_qspi_apb_controller_enable(reg_base);
 263         return;
 264 }
 265
 266 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
 267         unsigned int ref_clk_hz, unsigned int sclk_hz)
 268 {
 269         unsigned int reg;
 270         unsigned int div;
 271
 272         cadence_qspi_apb_controller_disable(reg_base);
 273         reg = readl(reg_base + CQSPI_REG_CONFIG);
 274         reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
 275
 276         div = ref_clk_hz / sclk_hz;
 277
 278         if (div > 32)
 279                 div = 32;
 280
 281         /* Check if even number. */
 282         if ((div & 1)) {
 283                 div = (div / 2);
 284         } else {
 285                 if (ref_clk_hz % sclk_hz)
 286                         /* ensure generated SCLK doesn't exceed user
 287                         specified sclk_hz */
 288                         div = (div / 2);
 289                 else
 290                         div = (div / 2) - 1;
 291         }
 292
 293         debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
 294               ref_clk_hz, sclk_hz, div);
 295
 296         div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 297         reg |= div;
 298         writel(reg, reg_base + CQSPI_REG_CONFIG);
 299
 300         cadence_qspi_apb_controller_enable(reg_base);
 301         return;
 302 }
 303
 304 void cadence_qspi_apb_set_clk_mode(void *reg_base,
 305         unsigned int clk_pol, unsigned int clk_pha)
 306 {
 307         unsigned int reg;
 308
 309         cadence_qspi_apb_controller_disable(reg_base);
 310         reg = readl(reg_base + CQSPI_REG_CONFIG);
 311         reg &= ~(1 <<
 312                 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
 313
 314         reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
 315         reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
 316
 317         writel(reg, reg_base + CQSPI_REG_CONFIG);
 318
 319         cadence_qspi_apb_controller_enable(reg_base);
 320         return;
 321 }
 322
 323 void cadence_qspi_apb_chipselect(void *reg_base,
 324         unsigned int chip_select, unsigned int decoder_enable)
 325 {
 326         unsigned int reg;
 327
 328         cadence_qspi_apb_controller_disable(reg_base);
 329
 330         debug("%s : chipselect %d decode %d\n", __func__, chip_select,
 331               decoder_enable);
 332
 333         reg = readl(reg_base + CQSPI_REG_CONFIG);
 334         /* docoder */
 335         if (decoder_enable) {
 336                 reg |= CQSPI_REG_CONFIG_DECODE_MASK;
 337         } else {
 338                 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
 339                 /* Convert CS if without decoder.
 340                  * CS0 to 4b'1110
 341                  * CS1 to 4b'1101
 342                  * CS2 to 4b'1011
 343                  * CS3 to 4b'0111
 344                  */
 345                 chip_select = 0xF & ~(1 << chip_select);
 346         }
 347
 348         reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
 349                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
 350         reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
 351                         << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
 352         writel(reg, reg_base + CQSPI_REG_CONFIG);
 353
 354         cadence_qspi_apb_controller_enable(reg_base);
 355         return;
 356 }
 357
 358 void cadence_qspi_apb_delay(void *reg_base,
 359         unsigned int ref_clk, unsigned int sclk_hz,
 360         unsigned int tshsl_ns, unsigned int tsd2d_ns,
 361         unsigned int tchsh_ns, unsigned int tslch_ns)
 362 {
 363         unsigned int ref_clk_ns;
 364         unsigned int sclk_ns;
 365         unsigned int tshsl, tchsh, tslch, tsd2d;
 366         unsigned int reg;
 367
 368         cadence_qspi_apb_controller_disable(reg_base);
 369
 370         /* Convert to ns. */
 371         ref_clk_ns = (1000000000) / ref_clk;
 372
 373         /* Convert to ns. */
 374         sclk_ns = (1000000000) / sclk_hz;
 375
 376         /* Plus 1 to round up 1 clock cycle. */
 377         tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
 378         tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
 379         tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
 380         tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
 381
 382         reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
 383                         << CQSPI_REG_DELAY_TSHSL_LSB);
 384         reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
 385                         << CQSPI_REG_DELAY_TCHSH_LSB);
 386         reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
 387                         << CQSPI_REG_DELAY_TSLCH_LSB);
 388         reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
 389                         << CQSPI_REG_DELAY_TSD2D_LSB);
 390         writel(reg, reg_base + CQSPI_REG_DELAY);
 391
 392         cadence_qspi_apb_controller_enable(reg_base);
 393         return;
 394 }
 395
 396 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
 397 {
 398         unsigned reg;
 399
 400         cadence_qspi_apb_controller_disable(plat->regbase);
 401
 402         /* Configure the device size and address bytes */
 403         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 404         /* Clear the previous value */
 405         reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
 406         reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
 407         reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
 408         reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
 409         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 410
 411         /* Configure the remap address register, no remap */
 412         writel(0, plat->regbase + CQSPI_REG_REMAP);
 413
 414         /* Indirect mode configurations */
 415         writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION);
 416
 417         /* Disable all interrupts */
 418         writel(0, plat->regbase + CQSPI_REG_IRQMASK);
 419
 420         cadence_qspi_apb_controller_enable(plat->regbase);
 421         return;
 422 }
 423
 424 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
 425         unsigned int reg)
 426 {
 427         unsigned int retry = CQSPI_REG_RETRY;
 428
 429         /* Write the CMDCTRL without start execution. */
 430         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 431         /* Start execute */
 432         reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
 433         writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 434
 435         while (retry--) {
 436                 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
 437                 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
 438                         break;
 439                 udelay(1);
 440         }
 441
 442         if (!retry) {
 443                 printf("QSPI: flash command execution timeout\n");
 444                 return -EIO;
 445         }
 446
 447         /* Polling QSPI idle status. */
 448         if (!cadence_qspi_wait_idle(reg_base))
 449                 return -EIO;
 450
 451         return 0;
 452 }
 453
 454 /* For command RDID, RDSR. */
 455 int cadence_qspi_apb_command_read(void *reg_base,
 456         unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
 457         u8 *rxbuf)
 458 {
 459         unsigned int reg;
 460         unsigned int read_len;
 461         int status;
 462
 463         if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
 464                 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
 465                        cmdlen, rxlen);
 466                 return -EINVAL;
 467         }
 468
 469         reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 470
 471         reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
 472
 473         /* 0 means 1 byte. */
 474         reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
 475                 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
 476         status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 477         if (status != 0)
 478                 return status;
 479
 480         reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
 481
 482         /* Put the read value into rx_buf */
 483         read_len = (rxlen > 4) ? 4 : rxlen;
 484         memcpy(rxbuf, &reg, read_len);
 485         rxbuf += read_len;
 486
 487         if (rxlen > 4) {
 488                 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
 489
 490                 read_len = rxlen - read_len;
 491                 memcpy(rxbuf, &reg, read_len);
 492         }
 493         return 0;
 494 }
 495
 496 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
 497 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
 498         const u8 *cmdbuf, unsigned int txlen,  const u8 *txbuf)
 499 {
 500         unsigned int reg = 0;
 501         unsigned int addr_value;
 502         unsigned int wr_data;
 503         unsigned int wr_len;
 504
 505         if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
 506                 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
 507                        cmdlen, txlen);
 508                 return -EINVAL;
 509         }
 510
 511         reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
 512
 513         if (cmdlen == 4 || cmdlen == 5) {
 514                 /* Command with address */
 515                 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
 516                 /* Number of bytes to write. */
 517                 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
 518                         << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
 519                 /* Get address */
 520                 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
 521                         cmdlen >= 5 ? 4 : 3);
 522
 523                 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
 524         }
 525
 526         if (txlen) {
 527                 /* writing data = yes */
 528                 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
 529                 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
 530                         << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
 531
 532                 wr_len = txlen > 4 ? 4 : txlen;
 533                 memcpy(&wr_data, txbuf, wr_len);
 534                 writel(wr_data, reg_base +
 535                         CQSPI_REG_CMDWRITEDATALOWER);
 536
 537                 if (txlen > 4) {
 538                         txbuf += wr_len;
 539                         wr_len = txlen - wr_len;
 540                         memcpy(&wr_data, txbuf, wr_len);
 541                         writel(wr_data, reg_base +
 542                                 CQSPI_REG_CMDWRITEDATAUPPER);
 543                 }
 544         }
 545
 546         /* Execute the command */
 547         return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
 548 }
 549
 550 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
 551 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
 552         unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf)
 553 {
 554         unsigned int reg;
 555         unsigned int rd_reg;
 556         unsigned int addr_value;
 557         unsigned int dummy_clk;
 558         unsigned int dummy_bytes;
 559         unsigned int addr_bytes;
 560
 561         /*
 562          * Identify addr_byte. All NOR flash device drivers are using fast read
 563          * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
 564          * With that, the length is in value of 5 or 6. Only FRAM chip from
 565          * ramtron using normal read (which won't need dummy byte).
 566          * Unlikely NOR flash using normal read due to performance issue.
 567          */
 568         if (cmdlen >= 5)
 569                 /* to cater fast read where cmd + addr + dummy */
 570                 addr_bytes = cmdlen - 2;
 571         else
 572                 /* for normal read (only ramtron as of now) */
 573                 addr_bytes = cmdlen - 1;
 574
 575         /* Setup the indirect trigger address */
 576         writel((u32)plat->ahbbase,
 577                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 578
 579         /* Configure the opcode */
 580         rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
 581
 582         if (rx_width & SPI_RX_QUAD)
 583                 /* Instruction and address at DQ0, data at DQ0-3. */
 584                 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
 585
 586         /* Get address */
 587         addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 588         writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
 589
 590         /* The remaining lenght is dummy bytes. */
 591         dummy_bytes = cmdlen - addr_bytes - 1;
 592         if (dummy_bytes) {
 593                 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
 594                         dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
 595
 596                 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 597 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
 598                 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
 599 #else
 600                 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
 601 #endif
 602
 603                 /* Convert to clock cycles. */
 604                 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
 605                 /* Need to minus the mode byte (8 clocks). */
 606                 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
 607
 608                 if (dummy_clk)
 609                         rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
 610                                 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
 611         }
 612
 613         writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
 614
 615         /* set device size */
 616         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 617         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 618         reg |= (addr_bytes - 1);
 619         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 620         return 0;
 621 }
 622
 623 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
 624 {
 625         u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
 626         reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
 627         return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
 628 }
 629
 630 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
 631 {
 632         unsigned int timeout = 10000;
 633         u32 reg;
 634
 635         while (timeout--) {
 636                 reg = cadence_qspi_get_rd_sram_level(plat);
 637                 if (reg)
 638                         return reg;
 639                 udelay(1);
 640         }
 641
 642         return -ETIMEDOUT;
 643 }
 644
 645 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 646         unsigned int n_rx, u8 *rxbuf)
 647 {
 648         unsigned int remaining = n_rx;
 649         unsigned int bytes_to_read = 0;
 650         int ret;
 651
 652         writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
 653
 654         /* Start the indirect read transfer */
 655         writel(CQSPI_REG_INDIRECTRD_START_MASK,
 656                plat->regbase + CQSPI_REG_INDIRECTRD);
 657
 658         while (remaining > 0) {
 659                 ret = cadence_qspi_wait_for_data(plat);
 660                 if (ret < 0) {
 661                         printf("Indirect write timed out (%i)\n", ret);
 662                         goto failrd;
 663                 }
 664
 665                 bytes_to_read = ret;
 666
 667                 while (bytes_to_read != 0) {
 668                         bytes_to_read *= CQSPI_FIFO_WIDTH;
 669                         bytes_to_read = bytes_to_read > remaining ?
 670                                         remaining : bytes_to_read;
 671                         /* Handle non-4-byte aligned access to avoid data abort. */
 672                         if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
 673                                 readsb(plat->ahbbase, rxbuf, bytes_to_read);
 674                         else
 675                                 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
 676                         rxbuf += bytes_to_read;
 677                         remaining -= bytes_to_read;
 678                         bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
 679                 }
 680         }
 681
 682         /* Check indirect done status */
 683         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
 684                            CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
 685         if (ret) {
 686                 printf("Indirect read completion error (%i)\n", ret);
 687                 goto failrd;
 688         }
 689
 690         /* Clear indirect completion status */
 691         writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
 692                plat->regbase + CQSPI_REG_INDIRECTRD);
 693
 694         return 0;
 695
 696 failrd:
 697         /* Cancel the indirect read */
 698         writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
 699                plat->regbase + CQSPI_REG_INDIRECTRD);
 700         return ret;
 701 }
 702
 703 /* Opcode + Address (3/4 bytes) */
 704 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
 705         unsigned int cmdlen, const u8 *cmdbuf)
 706 {
 707         unsigned int reg;
 708         unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
 709
 710         if (cmdlen < 4 || cmdbuf == NULL) {
 711                 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
 712                        cmdlen, (unsigned int)cmdbuf);
 713                 return -EINVAL;
 714         }
 715         /* Setup the indirect trigger address */
 716         writel((u32)plat->ahbbase,
 717                plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
 718
 719         /* Configure the opcode */
 720         reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
 721         writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
 722
 723         /* Setup write address. */
 724         reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
 725         writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
 726
 727         reg = readl(plat->regbase + CQSPI_REG_SIZE);
 728         reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
 729         reg |= (addr_bytes - 1);
 730         writel(reg, plat->regbase + CQSPI_REG_SIZE);
 731         return 0;
 732 }
 733
 734 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 735         unsigned int n_tx, const u8 *txbuf)
 736 {
 737         unsigned int page_size = plat->page_size;
 738         unsigned int remaining = n_tx;
 739         unsigned int write_bytes;
 740         int ret;
 741
 742         /* Configure the indirect read transfer bytes */
 743         writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
 744
 745         /* Start the indirect write transfer */
 746         writel(CQSPI_REG_INDIRECTWR_START_MASK,
 747                plat->regbase + CQSPI_REG_INDIRECTWR);
 748
 749         while (remaining > 0) {
 750                 write_bytes = remaining > page_size ? page_size : remaining;
 751                 /* Handle non-4-byte aligned access to avoid data abort. */
 752                 if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
 753                         writesb(plat->ahbbase, txbuf, write_bytes);
 754                 else
 755                         writesl(plat->ahbbase, txbuf, write_bytes >> 2);
 756
 757                 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
 758                                    CQSPI_REG_SDRAMLEVEL_WR_MASK <<
 759                                    CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
 760                 if (ret) {
 761                         printf("Indirect write timed out (%i)\n", ret);
 762                         goto failwr;
 763                 }
 764
 765                 txbuf += write_bytes;
 766                 remaining -= write_bytes;
 767         }
 768
 769         /* Check indirect done status */
 770         ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
 771                            CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
 772         if (ret) {
 773                 printf("Indirect write completion error (%i)\n", ret);
 774                 goto failwr;
 775         }
 776
 777         /* Clear indirect completion status */
 778         writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
 779                plat->regbase + CQSPI_REG_INDIRECTWR);
 780         return 0;
 781
 782 failwr:
 783         /* Cancel the indirect write */
 784         writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
 785                plat->regbase + CQSPI_REG_INDIRECTWR);
 786         return ret;
 787 }
 788
 789 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
 790 {
 791         unsigned int reg;
 792
 793         /* enter XiP mode immediately and enable direct mode */
 794         reg = readl(reg_base + CQSPI_REG_CONFIG);
 795         reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
 796         reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
 797         reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
 798         writel(reg, reg_base + CQSPI_REG_CONFIG);
 799
 800         /* keep the XiP mode */
 801         writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
 802
 803         /* Enable mode bit at devrd */
 804         reg = readl(reg_base + CQSPI_REG_RD_INSTR);
 805         reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
 806         writel(reg, reg_base + CQSPI_REG_RD_INSTR);
 807 }