2 * SPI Driver for EP93xx
4 * Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
6 * Inspired form linux kernel driver and atmel uboot driver
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/ep93xx.h>
20 #define BIT(x) (1<<(x))
21 #define SSPBASE SPI_BASE
24 #define SSPCR0_MODE_SHIFT 6
25 #define SSPCR0_SCR_SHIFT 8
26 #define SSPCR0_SPH BIT(7)
27 #define SSPCR0_SPO BIT(6)
28 #define SSPCR0_FRF_SPI 0
29 #define SSPCR0_DSS_8BIT 7
32 #define SSPCR1_RIE BIT(0)
33 #define SSPCR1_TIE BIT(1)
34 #define SSPCR1_RORIE BIT(2)
35 #define SSPCR1_LBM BIT(3)
36 #define SSPCR1_SSE BIT(4)
37 #define SSPCR1_MS BIT(5)
38 #define SSPCR1_SOD BIT(6)
43 #define SSPSR_TFE BIT(0)
44 #define SSPSR_TNF BIT(1)
45 #define SSPSR_RNE BIT(2)
46 #define SSPSR_RFF BIT(3)
47 #define SSPSR_BSY BIT(4)
48 #define SSPCPSR 0x0010
51 #define SSPIIR_RIS BIT(0)
52 #define SSPIIR_TIS BIT(1)
53 #define SSPIIR_RORIS BIT(2)
56 #define SSPCLOCK 14745600
57 #define SSP_MAX_RATE (SSPCLOCK / 2)
58 #define SSP_MIN_RATE (SSPCLOCK / (254 * 256))
60 /* timeout in milliseconds */
62 /* maximum depth of RX/TX FIFO */
63 #define SPI_FIFO_SIZE 8
65 struct ep93xx_spi_slave {
66 struct spi_slave slave;
72 static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave)
74 return container_of(slave, struct ep93xx_spi_slave, slave);
81 static inline void ep93xx_spi_write_u8(u16 reg, u8 value)
83 writel(value, (unsigned int *)(SSPBASE + reg));
86 static inline u8 ep93xx_spi_read_u8(u16 reg)
88 return readl((unsigned int *)(SSPBASE + reg));
91 static inline void ep93xx_spi_write_u16(u16 reg, u16 value)
93 writel(value, (unsigned int *)(SSPBASE + reg));
96 static inline u16 ep93xx_spi_read_u16(u16 reg)
98 return (u16)readl((unsigned int *)(SSPBASE + reg));
101 static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode,
102 struct ep93xx_spi_slave *slave)
106 if (rate > SSP_MAX_RATE)
109 if (rate < SSP_MIN_RATE)
112 /* Calculate divisors so that we can get speed according the
114 * rate = spi_clock_rate / (cpsr * (1 + scr))
116 * cpsr must be even number and starts from 2, scr can be any number
119 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
120 for (scr = 0; scr <= 255; scr++) {
121 if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) {
122 /* Set CHPA and CPOL, SPI format and 8bit */
123 unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) |
124 SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT;
126 sspcr0 |= SSPCR0_SPH;
128 sspcr0 |= SSPCR0_SPO;
130 slave->sspcr0 = sspcr0;
131 slave->sspcpsr = cpsr;
140 void spi_set_speed(struct spi_slave *slave, unsigned int hz)
142 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
144 unsigned int mode = 0;
145 if (as->sspcr0 & SSPCR0_SPH)
147 if (as->sspcr0 & SSPCR0_SPO)
150 ep93xx_spi_init_hw(hz, mode, as);
153 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
154 unsigned int max_hz, unsigned int mode)
156 struct ep93xx_spi_slave *as;
158 if (!spi_cs_is_valid(bus, cs))
161 as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs);
165 if (ep93xx_spi_init_hw(max_hz, mode, as)) {
173 void spi_free_slave(struct spi_slave *slave)
175 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
180 int spi_claim_bus(struct spi_slave *slave)
182 struct ep93xx_spi_slave *as = to_ep93xx_spi(slave);
184 /* Enable the SPI hardware */
185 ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE);
188 ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr);
189 ep93xx_spi_write_u16(SSPCR0, as->sspcr0);
191 debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n",
192 slave->cs, as->sspcpsr, as->sspcr0);
196 void spi_release_bus(struct spi_slave *slave)
198 /* Disable the SPI hardware */
199 ep93xx_spi_write_u8(SSPCR1, 0);
202 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
203 const void *dout, void *din, unsigned long flags)
209 const u8 *txp = dout;
213 debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n",
214 slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen);
218 /* Finish any previously submitted transfers */
222 /* Errors always terminate an ongoing transfer */
223 flags |= SPI_XFER_END;
230 if (flags & SPI_XFER_BEGIN) {
232 while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE))
233 ep93xx_spi_read_u8(SSPDR);
235 spi_cs_activate(slave);
238 for (len_tx = 0, len_rx = 0; len_rx < len; ) {
239 status = ep93xx_spi_read_u8(SSPSR);
241 if ((len_tx < len) && (status & SSPSR_TNF)) {
247 ep93xx_spi_write_u8(SSPDR, value);
251 if (status & SSPSR_RNE) {
252 value = ep93xx_spi_read_u8(SSPDR);
261 if (flags & SPI_XFER_END) {
263 * Wait until the transfer is completely done before
267 status = ep93xx_spi_read_u8(SSPSR);
268 } while (status & SSPSR_BSY);
270 spi_cs_deactivate(slave);