2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Padmavathi Venna <padma.v@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch-exynos/spi.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 /* Information about each SPI controller */
24 enum periph_id periph_id;
25 s32 frequency; /* Default clock frequency, -1 for none */
26 struct exynos_spi *regs;
27 int inited; /* 1 if this bus is ready for use */
29 uint deactivate_delay_us; /* Delay to wait after deactivate */
32 /* A list of spi buses that we know about */
33 static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
34 static unsigned int bus_count;
36 struct exynos_spi_slave {
37 struct spi_slave slave;
38 struct exynos_spi *regs;
39 unsigned int freq; /* Default frequency */
41 enum periph_id periph_id; /* Peripheral ID for this device */
42 unsigned int fifo_size;
44 struct spi_bus *bus; /* Pointer to our SPI bus info */
45 ulong last_transaction_us; /* Time of last transaction end */
48 static struct spi_bus *spi_get_bus(unsigned dev_index)
50 if (dev_index < bus_count)
51 return &spi_bus[dev_index];
52 debug("%s: invalid bus %d", __func__, dev_index);
57 static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
59 return container_of(slave, struct exynos_spi_slave, slave);
63 * Setup the driver private data
65 * @param bus ID of the bus that the slave is attached to
66 * @param cs ID of the chip select connected to the slave
67 * @param max_hz Required spi frequency
68 * @param mode Required spi mode (clk polarity, clk phase and
70 * @return new device or NULL
72 struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
73 unsigned int max_hz, unsigned int mode)
75 struct exynos_spi_slave *spi_slave;
78 if (!spi_cs_is_valid(busnum, cs)) {
79 debug("%s: Invalid bus/chip select %d, %d\n", __func__,
84 spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
86 debug("%s: Could not allocate spi_slave\n", __func__);
90 bus = &spi_bus[busnum];
92 spi_slave->regs = bus->regs;
93 spi_slave->mode = mode;
94 spi_slave->periph_id = bus->periph_id;
95 if (bus->periph_id == PERIPH_ID_SPI1 ||
96 bus->periph_id == PERIPH_ID_SPI2)
97 spi_slave->fifo_size = 64;
99 spi_slave->fifo_size = 256;
101 spi_slave->skip_preamble = 0;
102 spi_slave->last_transaction_us = timer_get_us();
104 spi_slave->freq = bus->frequency;
106 spi_slave->freq = min(max_hz, spi_slave->freq);
108 return &spi_slave->slave;
112 * Free spi controller
114 * @param slave Pointer to spi_slave to which controller has to
117 void spi_free_slave(struct spi_slave *slave)
119 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
125 * Flush spi tx, rx fifos and reset the SPI controller
127 * @param slave Pointer to spi_slave to which controller has to
130 static void spi_flush_fifo(struct spi_slave *slave)
132 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
133 struct exynos_spi *regs = spi_slave->regs;
135 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
136 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
137 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
141 * Initialize the spi base registers, set the required clock frequency and
142 * initialize the gpios
144 * @param slave Pointer to spi_slave to which controller has to
146 * @return zero on success else a negative value
148 int spi_claim_bus(struct spi_slave *slave)
150 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
151 struct exynos_spi *regs = spi_slave->regs;
155 ret = set_spi_clk(spi_slave->periph_id,
158 debug("%s: Failed to setup spi clock\n", __func__);
162 exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
164 spi_flush_fifo(slave);
166 reg = readl(®s->ch_cfg);
167 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
169 if (spi_slave->mode & SPI_CPHA)
170 reg |= SPI_CH_CPHA_B;
172 if (spi_slave->mode & SPI_CPOL)
173 reg |= SPI_CH_CPOL_L;
175 writel(reg, ®s->ch_cfg);
176 writel(SPI_FB_DELAY_180, ®s->fb_clk);
182 * Reset the spi H/W and flush the tx and rx fifos
184 * @param slave Pointer to spi_slave to which controller has to
187 void spi_release_bus(struct spi_slave *slave)
189 spi_flush_fifo(slave);
192 static void spi_get_fifo_levels(struct exynos_spi *regs,
193 int *rx_lvl, int *tx_lvl)
195 uint32_t spi_sts = readl(®s->spi_sts);
197 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
198 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
202 * If there's something to transfer, do a software reset and set a
205 * @param regs SPI peripheral registers
206 * @param count Number of bytes to transfer
207 * @param step Number of bytes to transfer in each packet (1 or 4)
209 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
211 /* For word address we need to swap bytes */
213 setbits_le32(®s->mode_cfg,
214 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
216 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
217 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
218 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
220 /* Select byte access and clear the swap configuration */
221 clrbits_le32(®s->mode_cfg,
222 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
223 writel(0, ®s->swap_cfg);
226 assert(count && count < (1 << 16));
227 setbits_le32(®s->ch_cfg, SPI_CH_RST);
228 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
230 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
233 static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
234 void **dinp, void const **doutp, unsigned long flags)
236 struct exynos_spi *regs = spi_slave->regs;
238 const uchar *txp = *doutp;
240 uint out_bytes, in_bytes;
242 unsigned start = get_timer(0);
246 out_bytes = in_bytes = todo;
248 stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
249 !(spi_slave->mode & SPI_SLAVE);
252 * Try to transfer words if we can. This helps read performance at
253 * SPI clock speeds above about 20MHz.
256 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
257 !spi_slave->skip_preamble)
261 * If there's something to send, do a software reset and set a
264 spi_request_bytes(regs, todo, step);
267 * Bytes are transmitted/received in pairs. Wait to receive all the
268 * data because then transmission will be done as well.
275 /* Keep the fifos full/empty. */
276 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
279 * Don't completely fill the txfifo, since we don't want our
280 * rxfifo to overflow, and it may already contain data.
282 while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) {
286 temp = *(uint32_t *)txp;
289 writel(temp, ®s->tx_data);
295 if (rx_lvl >= step) {
296 while (rx_lvl >= step) {
297 temp = readl(®s->rx_data);
298 if (spi_slave->skip_preamble) {
299 if (temp == SPI_PREAMBLE_END_BYTE) {
300 spi_slave->skip_preamble = 0;
304 if (rxp || stopping) {
313 } else if (!toread) {
315 * We have run out of input data, but haven't read
316 * enough bytes after the preamble yet. Read some more,
317 * and make sure that we transmit dummy bytes too, to
321 out_bytes = in_bytes;
324 spi_request_bytes(regs, toread, step);
326 if (spi_slave->skip_preamble && get_timer(start) > 100) {
327 printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
328 in_bytes, out_bytes);
340 * Transfer and receive data
342 * @param slave Pointer to spi_slave to which controller has to
344 * @param bitlen No of bits to tranfer or receive
345 * @param dout Pointer to transfer buffer
346 * @param din Pointer to receive buffer
347 * @param flags Flags for transfer begin and end
348 * @return zero on success else a negative value
350 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
351 void *din, unsigned long flags)
353 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
358 /* spi core configured to do 8 bit transfers */
360 debug("Non byte aligned SPI transfer.\n");
364 /* Start the transaction, if necessary. */
365 if ((flags & SPI_XFER_BEGIN))
366 spi_cs_activate(slave);
369 * Exynos SPI limits each transfer to 65535 transfers. To keep
370 * things simple, allow a maximum of 65532 bytes. We could allow
371 * more in word mode, but the performance difference is small.
373 bytelen = bitlen / 8;
374 for (upto = 0; !ret && upto < bytelen; upto += todo) {
375 todo = min(bytelen - upto, (1 << 16) - 4);
376 ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
381 /* Stop the transaction, if necessary. */
382 if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
383 spi_cs_deactivate(slave);
384 if (spi_slave->skip_preamble) {
385 assert(!spi_slave->skip_preamble);
386 debug("Failed to complete premable transaction\n");
395 * Validates the bus and chip select numbers
397 * @param bus ID of the bus that the slave is attached to
398 * @param cs ID of the chip select connected to the slave
399 * @return one on success else zero
401 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
403 return spi_get_bus(bus) && cs == 0;
407 * Activate the CS by driving it LOW
409 * @param slave Pointer to spi_slave to which controller has to
412 void spi_cs_activate(struct spi_slave *slave)
414 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
416 /* If it's too soon to do another transaction, wait */
417 if (spi_slave->bus->deactivate_delay_us &&
418 spi_slave->last_transaction_us) {
419 ulong delay_us; /* The delay completed so far */
420 delay_us = timer_get_us() - spi_slave->last_transaction_us;
421 if (delay_us < spi_slave->bus->deactivate_delay_us)
422 udelay(spi_slave->bus->deactivate_delay_us - delay_us);
425 clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
426 debug("Activate CS, bus %d\n", spi_slave->slave.bus);
427 spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
429 /* Remember time of this transaction so we can honour the bus delay */
430 if (spi_slave->bus->deactivate_delay_us)
431 spi_slave->last_transaction_us = timer_get_us();
435 * Deactivate the CS by driving it HIGH
437 * @param slave Pointer to spi_slave to which controller has to
440 void spi_cs_deactivate(struct spi_slave *slave)
442 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
444 setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
445 debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
448 static inline struct exynos_spi *get_spi_base(int dev_index)
451 return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
453 return (struct exynos_spi *)samsung_get_base_spi_isp() +
458 * Read the SPI config from the device tree node.
460 * @param blob FDT blob to read from
461 * @param node Node offset to read from
462 * @param bus SPI bus structure to fill with information
463 * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
465 #ifdef CONFIG_OF_CONTROL
466 static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
469 bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
470 bus->periph_id = pinmux_decode_periph_id(blob, node);
472 if (bus->periph_id == PERIPH_ID_NONE) {
473 debug("%s: Invalid peripheral ID %d\n", __func__,
475 return -FDT_ERR_NOTFOUND;
478 /* Use 500KHz as a suitable default */
479 bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
481 bus->deactivate_delay_us = fdtdec_get_int(blob, node,
482 "spi-deactivate-delay", 0);
488 * Process a list of nodes, adding them to our list of SPI ports.
490 * @param blob fdt blob
491 * @param node_list list of nodes to process (any <=0 are ignored)
492 * @param count number of nodes to process
493 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
494 * @return 0 if ok, -1 on error
496 static int process_nodes(const void *blob, int node_list[], int count)
500 /* build the i2c_controllers[] for each controller */
501 for (i = 0; i < count; i++) {
502 int node = node_list[i];
509 if (spi_get_config(blob, node, bus)) {
510 printf("exynos spi_init: failed to decode bus %d\n",
515 debug("spi: controller bus %d at %p, periph_id %d\n",
516 i, bus->regs, bus->periph_id);
526 * Set up a new SPI slave for an fdt node
528 * @param blob Device tree blob
529 * @param node SPI peripheral node to use
530 * @return 0 if ok, -1 on error
532 struct spi_slave *spi_setup_slave_fdt(const void *blob, int node,
533 unsigned int cs, unsigned int max_hz, unsigned int mode)
538 for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
539 if (bus->node == node)
540 return spi_setup_slave(i, cs, max_hz, mode);
543 debug("%s: Failed to find bus node %d\n", __func__, node);
547 /* Sadly there is no error return from this function */
552 #ifdef CONFIG_OF_CONTROL
553 int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
554 const void *blob = gd->fdt_blob;
556 count = fdtdec_find_aliases_for_id(blob, "spi",
557 COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
558 EXYNOS5_SPI_NUM_CONTROLLERS);
559 if (process_nodes(blob, node_list, count))
565 for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
566 bus = &spi_bus[count];
567 bus->regs = get_spi_base(count);
568 bus->periph_id = PERIPH_ID_SPI0 + count;
570 /* Although Exynos5 supports upto 50Mhz speed,
571 * we are setting it to 10Mhz for safe side
573 bus->frequency = 10000000;
576 bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;