2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * Chao Fu (B44548@freescale.com)
8 * Haikun Wang (B53464@freescale.com)
10 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/clock.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 /* fsl_dspi_platdata flags */
29 #define DSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0)
32 #define DSPI_IDLE_VAL 0x0
34 /* max chipselect signals number */
35 #define FSL_DSPI_MAX_CHIPSELECT 6
37 /* default SCK frequency, unit: HZ */
38 #define FSL_DSPI_DEFAULT_SCK_FREQ 10000000
40 /* tx/rx data wait timeout value, unit: us */
41 #define DSPI_TXRX_WAIT_TIMEOUT 1000000
43 /* CTAR register pre-configure value */
44 #define DSPI_CTAR_DEFAULT_VALUE (DSPI_CTAR_TRSZ(7) | \
45 DSPI_CTAR_PCSSCK_1CLK | \
48 DSPI_CTAR_CSSCK(0) | \
52 /* CTAR register pre-configure mask */
53 #define DSPI_CTAR_SET_MODE_MASK (DSPI_CTAR_TRSZ(15) | \
54 DSPI_CTAR_PCSSCK(3) | \
57 DSPI_CTAR_CSSCK(15) | \
62 * struct fsl_dspi_platdata - platform data for Freescale DSPI
64 * @flags: Flags for DSPI DSPI_FLAG_...
65 * @speed_hz: Default SCK frequency
66 * @num_chipselect: Number of DSPI chipselect signals
67 * @regs_addr: Base address of DSPI registers
69 struct fsl_dspi_platdata {
77 * struct fsl_dspi_priv - private data for Freescale DSPI
79 * @flags: Flags for DSPI DSPI_FLAG_...
80 * @mode: SPI mode to use for slave device (see SPI mode flags)
81 * @mcr_val: MCR register configure value
82 * @bus_clk: DSPI input clk frequency
83 * @speed_hz: Default SCK frequency
84 * @charbit: How many bits in every transfer
85 * @num_chipselect: Number of DSPI chipselect signals
86 * @ctar_val: CTAR register configure value of per chipselect slave device
87 * @regs: Point to DSPI register structure for I/O access
89 struct fsl_dspi_priv {
97 uint ctar_val[FSL_DSPI_MAX_CHIPSELECT];
101 #ifndef CONFIG_DM_SPI
103 struct spi_slave slave;
104 struct fsl_dspi_priv priv;
108 __weak void cpu_dspi_port_conf(void)
112 __weak int cpu_dspi_claim_bus(uint bus, uint cs)
117 __weak void cpu_dspi_release_bus(uint bus, uint cs)
121 static uint dspi_read32(uint flags, uint *addr)
123 return flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
124 in_be32(addr) : in_le32(addr);
127 static void dspi_write32(uint flags, uint *addr, uint val)
129 flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ?
130 out_be32(addr, val) : out_le32(addr, val);
133 static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt)
137 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
140 mcr_val |= DSPI_MCR_HALT;
142 mcr_val &= ~DSPI_MCR_HALT;
144 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
147 static void fsl_dspi_init_mcr(struct fsl_dspi_priv *priv, uint cfg_val)
149 /* halt DSPI module */
152 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val);
157 priv->mcr_val = cfg_val;
160 static void fsl_dspi_cfg_cs_active_state(struct fsl_dspi_priv *priv,
167 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
168 if (state & SPI_CS_HIGH)
169 /* CSx inactive state is low */
170 mcr_val &= ~DSPI_MCR_PCSIS(cs);
172 /* CSx inactive state is high */
173 mcr_val |= DSPI_MCR_PCSIS(cs);
174 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
179 static int fsl_dspi_cfg_ctar_mode(struct fsl_dspi_priv *priv,
184 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
186 bus_setup &= ~DSPI_CTAR_SET_MODE_MASK;
187 bus_setup |= priv->ctar_val[cs];
188 bus_setup &= ~(DSPI_CTAR_CPOL | DSPI_CTAR_CPHA | DSPI_CTAR_LSBFE);
191 bus_setup |= DSPI_CTAR_CPOL;
193 bus_setup |= DSPI_CTAR_CPHA;
194 if (mode & SPI_LSB_FIRST)
195 bus_setup |= DSPI_CTAR_LSBFE;
197 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
200 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) &
201 DSPI_CTAR_TRSZ(15)) == DSPI_CTAR_TRSZ(15)) ? 16 : 8;
206 static void fsl_dspi_clr_fifo(struct fsl_dspi_priv *priv)
211 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr);
212 /* flush RX and TX FIFO */
213 mcr_val |= (DSPI_MCR_CTXF | DSPI_MCR_CRXF);
214 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
218 static void dspi_tx(struct fsl_dspi_priv *priv, u32 ctrl, u16 data)
220 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
222 /* wait for empty entries in TXFIFO or timeout */
223 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 &&
228 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data));
230 debug("dspi_tx: waiting timeout!\n");
233 static u16 dspi_rx(struct fsl_dspi_priv *priv)
235 int timeout = DSPI_TXRX_WAIT_TIMEOUT;
237 /* wait for valid entries in RXFIFO or timeout */
238 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 &&
243 return (u16)DSPI_RFR_RXDATA(
244 dspi_read32(priv->flags, &priv->regs->rfr));
246 debug("dspi_rx: waiting timeout!\n");
251 static int dspi_xfer(struct fsl_dspi_priv *priv, uint cs, unsigned int bitlen,
252 const void *dout, void *din, unsigned long flags)
254 u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
255 u8 *spi_rd = NULL, *spi_wr = NULL;
257 uint len = bitlen >> 3;
259 if (priv->charbit == 16) {
261 spi_wr16 = (u16 *)dout;
262 spi_rd16 = (u16 *)din;
268 if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)
269 ctrl |= DSPI_TFR_CONT;
271 ctrl = ctrl & DSPI_TFR_CONT;
272 ctrl = ctrl | DSPI_TFR_CTAS(0) | DSPI_TFR_PCS(cs);
275 int tmp_len = len - 1;
278 if (priv->charbit == 16)
279 dspi_tx(priv, ctrl, *spi_wr16++);
281 dspi_tx(priv, ctrl, *spi_wr++);
286 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
287 if (priv->charbit == 16)
288 *spi_rd16++ = dspi_rx(priv);
290 *spi_rd++ = dspi_rx(priv);
294 len = 1; /* remaining byte */
297 if ((flags & SPI_XFER_END) == SPI_XFER_END)
298 ctrl &= ~DSPI_TFR_CONT;
302 if (priv->charbit == 16)
303 dspi_tx(priv, ctrl, *spi_wr16);
305 dspi_tx(priv, ctrl, *spi_wr);
310 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
311 if (priv->charbit == 16)
312 *spi_rd16 = dspi_rx(priv);
314 *spi_rd = dspi_rx(priv);
318 dspi_tx(priv, ctrl, DSPI_IDLE_VAL);
326 * Calculate the divide value between input clk frequency and expected SCK frequency
327 * Formula: SCK = (clkrate/pbr) x ((1+dbr)/br)
328 * Dbr: use default value 0
330 * @pbr: return Baud Rate Prescaler value
331 * @br: return Baud Rate Scaler value
332 * @speed_hz: expected SCK frequency
333 * @clkrate: input clk frequency
335 static int fsl_dspi_hz_to_spi_baud(int *pbr, int *br,
336 int speed_hz, uint clkrate)
338 /* Valid baud rate pre-scaler values */
339 int pbr_tbl[4] = {2, 3, 5, 7};
340 int brs[16] = {2, 4, 6, 8,
342 256, 512, 1024, 2048,
343 4096, 8192, 16384, 32768};
344 int temp, i = 0, j = 0;
346 temp = clkrate / speed_hz;
348 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
349 for (j = 0; j < ARRAY_SIZE(brs); j++) {
350 if (pbr_tbl[i] * brs[j] >= temp) {
357 debug("Can not find valid baud rate,speed_hz is %d, ", speed_hz);
358 debug("clkrate is %d, we use the max prescaler value.\n", clkrate);
360 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
361 *br = ARRAY_SIZE(brs) - 1;
365 static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
369 int best_i, best_j, bus_clk;
371 bus_clk = priv->bus_clk;
373 debug("DSPI set_speed: expected SCK speed %u, bus_clk %u.\n",
376 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]);
377 bus_setup &= ~(DSPI_CTAR_DBR | DSPI_CTAR_PBR(0x3) | DSPI_CTAR_BR(0xf));
379 ret = fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
381 speed = priv->speed_hz;
382 debug("DSPI set_speed use default SCK rate %u.\n", speed);
383 fsl_dspi_hz_to_spi_baud(&best_i, &best_j, speed, bus_clk);
386 bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
387 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup);
389 priv->speed_hz = speed;
393 #ifndef CONFIG_DM_SPI
399 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
401 if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))
407 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
408 unsigned int max_hz, unsigned int mode)
410 struct fsl_dspi *dspi;
413 dspi = spi_alloc_slave(struct fsl_dspi, bus, cs);
417 cpu_dspi_port_conf();
419 #ifdef CONFIG_SYS_FSL_DSPI_BE
420 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
423 dspi->priv.regs = (struct dspi *)MMAP_DSPI;
426 dspi->priv.bus_clk = gd->bus_clk;
428 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK);
430 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ;
432 /* default: all CS signals inactive state is high */
433 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
434 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
435 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val);
437 for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++)
438 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE;
440 #ifdef CONFIG_SYS_DSPI_CTAR0
441 if (FSL_DSPI_MAX_CHIPSELECT > 0)
442 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0;
444 #ifdef CONFIG_SYS_DSPI_CTAR1
445 if (FSL_DSPI_MAX_CHIPSELECT > 1)
446 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1;
448 #ifdef CONFIG_SYS_DSPI_CTAR2
449 if (FSL_DSPI_MAX_CHIPSELECT > 2)
450 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2;
452 #ifdef CONFIG_SYS_DSPI_CTAR3
453 if (FSL_DSPI_MAX_CHIPSELECT > 3)
454 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3;
456 #ifdef CONFIG_SYS_DSPI_CTAR4
457 if (FSL_DSPI_MAX_CHIPSELECT > 4)
458 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4;
460 #ifdef CONFIG_SYS_DSPI_CTAR5
461 if (FSL_DSPI_MAX_CHIPSELECT > 5)
462 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5;
464 #ifdef CONFIG_SYS_DSPI_CTAR6
465 if (FSL_DSPI_MAX_CHIPSELECT > 6)
466 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6;
468 #ifdef CONFIG_SYS_DSPI_CTAR7
469 if (FSL_DSPI_MAX_CHIPSELECT > 7)
470 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7;
473 fsl_dspi_cfg_speed(&dspi->priv, max_hz);
475 /* configure transfer mode */
476 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode);
478 /* configure active state of CSX */
479 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode);
484 void spi_free_slave(struct spi_slave *slave)
489 int spi_claim_bus(struct spi_slave *slave)
492 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
494 cpu_dspi_claim_bus(slave->bus, slave->cs);
496 fsl_dspi_clr_fifo(&dspi->priv);
498 /* check module TX and RX status */
499 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr);
500 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
501 debug("DSPI RX/TX not ready!\n");
508 void spi_release_bus(struct spi_slave *slave)
510 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
512 dspi_halt(&dspi->priv, 1);
513 cpu_dspi_release_bus(slave->bus.slave->cs);
516 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
517 void *din, unsigned long flags)
519 struct fsl_dspi *dspi = (struct fsl_dspi *)slave;
520 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags);
523 static int fsl_dspi_child_pre_probe(struct udevice *dev)
525 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
526 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
528 if (slave_plat->cs >= priv->num_chipselect) {
529 debug("DSPI invalid chipselect number %d(max %d)!\n",
530 slave_plat->cs, priv->num_chipselect - 1);
534 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
536 debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
537 slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
542 static int fsl_dspi_probe(struct udevice *bus)
544 struct fsl_dspi_platdata *plat = dev_get_platdata(bus);
545 struct fsl_dspi_priv *priv = dev_get_priv(bus);
546 struct dm_spi_bus *dm_spi_bus;
549 dm_spi_bus = bus->uclass_priv;
551 /* cpu speical pin muxing configure */
552 cpu_dspi_port_conf();
554 /* get input clk frequency */
555 priv->regs = (struct dspi *)plat->regs_addr;
556 priv->flags = plat->flags;
558 priv->bus_clk = gd->bus_clk;
560 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK);
562 priv->num_chipselect = plat->num_chipselect;
563 priv->speed_hz = plat->speed_hz;
564 /* frame data length in bits, default 8bits */
567 dm_spi_bus->max_hz = plat->speed_hz;
569 /* default: all CS signals inactive state is high */
570 mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
571 DSPI_MCR_CRXF | DSPI_MCR_CTXF;
572 fsl_dspi_init_mcr(priv, mcr_cfg_val);
574 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);
579 static int fsl_dspi_claim_bus(struct udevice *dev)
582 struct fsl_dspi_priv *priv;
583 struct udevice *bus = dev->parent;
584 struct dm_spi_slave_platdata *slave_plat =
585 dev_get_parent_platdata(dev);
587 priv = dev_get_priv(bus);
589 /* processor special preparation work */
590 cpu_dspi_claim_bus(bus->seq, slave_plat->cs);
592 /* configure transfer mode */
593 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode);
595 /* configure active state of CSX */
596 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs,
599 fsl_dspi_clr_fifo(priv);
601 /* check module TX and RX status */
602 sr_val = dspi_read32(priv->flags, &priv->regs->sr);
603 if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) {
604 debug("DSPI RX/TX not ready!\n");
611 static int fsl_dspi_release_bus(struct udevice *dev)
613 struct udevice *bus = dev->parent;
614 struct fsl_dspi_priv *priv = dev_get_priv(bus);
615 struct dm_spi_slave_platdata *slave_plat =
616 dev_get_parent_platdata(dev);
621 /* processor special release work */
622 cpu_dspi_release_bus(bus->seq, slave_plat->cs);
628 * This function doesn't do anything except help with debugging
630 static int fsl_dspi_bind(struct udevice *bus)
632 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq);
636 static int fsl_dspi_ofdata_to_platdata(struct udevice *bus)
639 struct fsl_dspi_platdata *plat = bus->platdata;
640 const void *blob = gd->fdt_blob;
641 int node = dev_of_offset(bus);
643 if (fdtdec_get_bool(blob, node, "big-endian"))
644 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
646 plat->num_chipselect =
647 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
649 addr = devfdt_get_addr(bus);
650 if (addr == FDT_ADDR_T_NONE) {
651 debug("DSPI: Can't get base address or size\n");
654 plat->regs_addr = addr;
656 plat->speed_hz = fdtdec_get_int(blob,
657 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ);
659 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n",
660 &plat->regs_addr, plat->speed_hz,
661 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le",
662 plat->num_chipselect);
667 static int fsl_dspi_xfer(struct udevice *dev, unsigned int bitlen,
668 const void *dout, void *din, unsigned long flags)
670 struct fsl_dspi_priv *priv;
671 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
675 priv = dev_get_priv(bus);
677 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags);
680 static int fsl_dspi_set_speed(struct udevice *bus, uint speed)
682 struct fsl_dspi_priv *priv = dev_get_priv(bus);
684 return fsl_dspi_cfg_speed(priv, speed);
687 static int fsl_dspi_set_mode(struct udevice *bus, uint mode)
689 struct fsl_dspi_priv *priv = dev_get_priv(bus);
691 debug("DSPI set_mode: mode 0x%x.\n", mode);
694 * We store some chipselect special configure value in priv->ctar_val,
695 * and we can't get the correct chipselect number here,
696 * so just store mode value.
697 * Do really configuration when claim_bus.
704 static const struct dm_spi_ops fsl_dspi_ops = {
705 .claim_bus = fsl_dspi_claim_bus,
706 .release_bus = fsl_dspi_release_bus,
707 .xfer = fsl_dspi_xfer,
708 .set_speed = fsl_dspi_set_speed,
709 .set_mode = fsl_dspi_set_mode,
712 static const struct udevice_id fsl_dspi_ids[] = {
713 { .compatible = "fsl,vf610-dspi" },
717 U_BOOT_DRIVER(fsl_dspi) = {
720 .of_match = fsl_dspi_ids,
721 .ops = &fsl_dspi_ops,
722 .ofdata_to_platdata = fsl_dspi_ofdata_to_platdata,
723 .platdata_auto_alloc_size = sizeof(struct fsl_dspi_platdata),
724 .priv_auto_alloc_size = sizeof(struct fsl_dspi_priv),
725 .probe = fsl_dspi_probe,
726 .child_pre_probe = fsl_dspi_child_pre_probe,
727 .bind = fsl_dspi_bind,