git.sur5r.net Git - u-boot/blob - drivers/spi/fsl_qspi.c

   1 /*
   2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <spi.h>
  12 #include <asm/io.h>
  13 #include <linux/sizes.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #ifdef CONFIG_MX6SX
  23 #define TX_BUFFER_SIZE          0x200
  24 #else
  25 #define TX_BUFFER_SIZE          0x40
  26 #endif
  27
  28 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  29
  30 #define FLASH_STATUS_WEL        0x02
  31
  32 /* SEQID */
  33 #define SEQID_WREN              1
  34 #define SEQID_FAST_READ         2
  35 #define SEQID_RDSR              3
  36 #define SEQID_SE                4
  37 #define SEQID_CHIP_ERASE        5
  38 #define SEQID_PP                6
  39 #define SEQID_RDID              7
  40 #define SEQID_BE_4K             8
  41 #ifdef CONFIG_SPI_FLASH_BAR
  42 #define SEQID_BRRD              9
  43 #define SEQID_BRWR              10
  44 #define SEQID_RDEAR             11
  45 #define SEQID_WREAR             12
  46 #endif
  47 #define SEQID_WRAR              13
  48 #define SEQID_RDAR              14
  49
  50 /* QSPI CMD */
  51 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  52 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  53 #define QSPI_CMD_WREN           0x06    /* Write enable */
  54 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  55 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  56 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  57 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  58 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  59
  60 /* Used for Micron, winbond and Macronix flashes */
  61 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  62 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  63
  64 /* Used for Spansion flashes only. */
  65 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  66 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  67
  68 /* Used for Spansion S25FS-S family flash only. */
  69 #define QSPI_CMD_RDAR           0x65    /* Read any device register */
  70 #define QSPI_CMD_WRAR           0x71    /* Write any device register */
  71
  72 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  73 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  74 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  75 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  76
  77 /* fsl_qspi_platdata flags */
  78 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  79
  80 /* default SCK frequency, unit: HZ */
  81 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  82
  83 /* QSPI max chipselect signals number */
  84 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  85
  86 #ifdef CONFIG_DM_SPI
  87 /**
  88  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  89  *
  90  * @flags: Flags for QSPI QSPI_FLAG_...
  91  * @speed_hz: Default SCK frequency
  92  * @reg_base: Base address of QSPI registers
  93  * @amba_base: Base address of QSPI memory mapping
  94  * @amba_total_size: size of QSPI memory mapping
  95  * @flash_num: Number of active slave devices
  96  * @num_chipselect: Number of QSPI chipselect signals
  97  */
  98 struct fsl_qspi_platdata {
  99         u32 flags;
 100         u32 speed_hz;
 101         fdt_addr_t reg_base;
 102         fdt_addr_t amba_base;
 103         fdt_size_t amba_total_size;
 104         u32 flash_num;
 105         u32 num_chipselect;
 106 };
 107 #endif
 108
 109 /**
 110  * struct fsl_qspi_priv - private data for Freescale QSPI
 111  *
 112  * @flags: Flags for QSPI QSPI_FLAG_...
 113  * @bus_clk: QSPI input clk frequency
 114  * @speed_hz: Default SCK frequency
 115  * @cur_seqid: current LUT table sequence id
 116  * @sf_addr: flash access offset
 117  * @amba_base: Base address of QSPI memory mapping of every CS
 118  * @amba_total_size: size of QSPI memory mapping
 119  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 120  * @flash_num: Number of active slave devices
 121  * @num_chipselect: Number of QSPI chipselect signals
 122  * @regs: Point to QSPI register structure for I/O access
 123  */
 124 struct fsl_qspi_priv {
 125         u32 flags;
 126         u32 bus_clk;
 127         u32 speed_hz;
 128         u32 cur_seqid;
 129         u32 sf_addr;
 130         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 131         u32 amba_total_size;
 132         u32 cur_amba_base;
 133         u32 flash_num;
 134         u32 num_chipselect;
 135         struct fsl_qspi_regs *regs;
 136 };
 137
 138 #ifndef CONFIG_DM_SPI
 139 struct fsl_qspi {
 140         struct spi_slave slave;
 141         struct fsl_qspi_priv priv;
 142 };
 143 #endif
 144
 145 static u32 qspi_read32(u32 flags, u32 *addr)
 146 {
 147         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 148                 in_be32(addr) : in_le32(addr);
 149 }
 150
 151 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 152 {
 153         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 154                 out_be32(addr, val) : out_le32(addr, val);
 155 }
 156
 157 /* QSPI support swapping the flash read/write data
 158  * in hardware for LS102xA, but not for VF610 */
 159 static inline u32 qspi_endian_xchg(u32 data)
 160 {
 161 #ifdef CONFIG_VF610
 162         return swab32(data);
 163 #else
 164         return data;
 165 #endif
 166 }
 167
 168 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 169 {
 170         struct fsl_qspi_regs *regs = priv->regs;
 171         u32 lut_base;
 172
 173         /* Unlock the LUT */
 174         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 175         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 176
 177         /* Write Enable */
 178         lut_base = SEQID_WREN * 4;
 179         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 180                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 181         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 182         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 183         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 184
 185         /* Fast Read */
 186         lut_base = SEQID_FAST_READ * 4;
 187 #ifdef CONFIG_SPI_FLASH_BAR
 188         qspi_write32(priv->flags, &regs->lut[lut_base],
 189                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 190                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 191                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 192 #else
 193         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 194                 qspi_write32(priv->flags, &regs->lut[lut_base],
 195                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 196                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 197                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 198         else
 199                 qspi_write32(priv->flags, &regs->lut[lut_base],
 200                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 201                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 202                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 203                              INSTR1(LUT_ADDR));
 204 #endif
 205         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 206                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 207                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 208                      INSTR1(LUT_READ));
 209         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 210         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 211
 212         /* Read Status */
 213         lut_base = SEQID_RDSR * 4;
 214         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 215                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 216                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 217         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 218         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 219         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 220
 221         /* Erase a sector */
 222         lut_base = SEQID_SE * 4;
 223 #ifdef CONFIG_SPI_FLASH_BAR
 224         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 225                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 226                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 227 #else
 228         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 229                 qspi_write32(priv->flags, &regs->lut[lut_base],
 230                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 231                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 232                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 233         else
 234                 qspi_write32(priv->flags, &regs->lut[lut_base],
 235                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 236                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 237                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 238 #endif
 239         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 240         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 241         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 242
 243         /* Erase the whole chip */
 244         lut_base = SEQID_CHIP_ERASE * 4;
 245         qspi_write32(priv->flags, &regs->lut[lut_base],
 246                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 247                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 248         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 249         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 250         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 251
 252         /* Page Program */
 253         lut_base = SEQID_PP * 4;
 254 #ifdef CONFIG_SPI_FLASH_BAR
 255         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 256                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 257                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 258 #else
 259         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 260                 qspi_write32(priv->flags, &regs->lut[lut_base],
 261                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 262                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 263                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 264         else
 265                 qspi_write32(priv->flags, &regs->lut[lut_base],
 266                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 267                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 268                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 269 #endif
 270 #ifdef CONFIG_MX6SX
 271         /*
 272          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 273          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 274          */
 275         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 276                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 277 #else
 278         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 279                      OPRND0(TX_BUFFER_SIZE) |
 280                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 281 #endif
 282         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 283         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 284
 285         /* READ ID */
 286         lut_base = SEQID_RDID * 4;
 287         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 288                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 289                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 290         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 291         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 292         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 293
 294         /* SUB SECTOR 4K ERASE */
 295         lut_base = SEQID_BE_4K * 4;
 296         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 297                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 298                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 299
 300 #ifdef CONFIG_SPI_FLASH_BAR
 301         /*
 302          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 303          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 304          * initialization.
 305          */
 306         lut_base = SEQID_BRRD * 4;
 307         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 308                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 309                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 310
 311         lut_base = SEQID_BRWR * 4;
 312         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 313                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 314                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 315
 316         lut_base = SEQID_RDEAR * 4;
 317         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 318                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 319                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 320
 321         lut_base = SEQID_WREAR * 4;
 322         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 323                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 324                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 325 #endif
 326
 327         /*
 328          * Read any device register.
 329          * Used for Spansion S25FS-S family flash only.
 330          */
 331         lut_base = SEQID_RDAR * 4;
 332         qspi_write32(priv->flags, &regs->lut[lut_base],
 333                      OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
 334                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 335                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 336         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 337                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 338                      OPRND1(1) | PAD1(LUT_PAD1) |
 339                      INSTR1(LUT_READ));
 340
 341         /*
 342          * Write any device register.
 343          * Used for Spansion S25FS-S family flash only.
 344          */
 345         lut_base = SEQID_WRAR * 4;
 346         qspi_write32(priv->flags, &regs->lut[lut_base],
 347                      OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
 348                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 349                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 350         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 351                      OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 352
 353         /* Lock the LUT */
 354         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 355         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 356 }
 357
 358 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 359 /*
 360  * If we have changed the content of the flash by writing or erasing,
 361  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 362  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 363  * domain at the same time.
 364  */
 365 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 366 {
 367         struct fsl_qspi_regs *regs = priv->regs;
 368         u32 reg;
 369
 370         reg = qspi_read32(priv->flags, &regs->mcr);
 371         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 372         qspi_write32(priv->flags, &regs->mcr, reg);
 373
 374         /*
 375          * The minimum delay : 1 AHB + 2 SFCK clocks.
 376          * Delay 1 us is enough.
 377          */
 378         udelay(1);
 379
 380         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 381         qspi_write32(priv->flags, &regs->mcr, reg);
 382 }
 383
 384 /* Read out the data from the AHB buffer. */
 385 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 386 {
 387         struct fsl_qspi_regs *regs = priv->regs;
 388         u32 mcr_reg;
 389         void *rx_addr = NULL;
 390
 391         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 392
 393         qspi_write32(priv->flags, &regs->mcr,
 394                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 395                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 396
 397         rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr);
 398         /* Read out the data directly from the AHB buffer. */
 399         memcpy(rxbuf, rx_addr, len);
 400
 401         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 402 }
 403
 404 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 405 {
 406         u32 reg, reg2;
 407         struct fsl_qspi_regs *regs = priv->regs;
 408
 409         reg = qspi_read32(priv->flags, &regs->mcr);
 410         /* Disable the module */
 411         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 412
 413         /* Set the Sampling Register for DDR */
 414         reg2 = qspi_read32(priv->flags, &regs->smpr);
 415         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 416         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 417         qspi_write32(priv->flags, &regs->smpr, reg2);
 418
 419         /* Enable the module again (enable the DDR too) */
 420         reg |= QSPI_MCR_DDR_EN_MASK;
 421         /* Enable bit 29 for imx6sx */
 422         reg |= BIT(29);
 423
 424         qspi_write32(priv->flags, &regs->mcr, reg);
 425 }
 426
 427 /*
 428  * There are two different ways to read out the data from the flash:
 429  *  the "IP Command Read" and the "AHB Command Read".
 430  *
 431  * The IC guy suggests we use the "AHB Command Read" which is faster
 432  * then the "IP Command Read". (What's more is that there is a bug in
 433  * the "IP Command Read" in the Vybrid.)
 434  *
 435  * After we set up the registers for the "AHB Command Read", we can use
 436  * the memcpy to read the data directly. A "missed" access to the buffer
 437  * causes the controller to clear the buffer, and use the sequence pointed
 438  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 439  */
 440 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 441 {
 442         struct fsl_qspi_regs *regs = priv->regs;
 443
 444         /* AHB configuration for access buffer 0/1/2 .*/
 445         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 446         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 447         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 448         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 449                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 450
 451         /* We only use the buffer3 */
 452         qspi_write32(priv->flags, &regs->buf0ind, 0);
 453         qspi_write32(priv->flags, &regs->buf1ind, 0);
 454         qspi_write32(priv->flags, &regs->buf2ind, 0);
 455
 456         /*
 457          * Set the default lut sequence for AHB Read.
 458          * Parallel mode is disabled.
 459          */
 460         qspi_write32(priv->flags, &regs->bfgencr,
 461                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 462
 463         /*Enable DDR Mode*/
 464         qspi_enable_ddr_mode(priv);
 465 }
 466 #endif
 467
 468 #ifdef CONFIG_SPI_FLASH_BAR
 469 /* Bank register read/write, EAR register read/write */
 470 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 471 {
 472         struct fsl_qspi_regs *regs = priv->regs;
 473         u32 reg, mcr_reg, data, seqid;
 474
 475         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 476         qspi_write32(priv->flags, &regs->mcr,
 477                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 478                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 479         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 480
 481         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 482
 483         if (priv->cur_seqid == QSPI_CMD_BRRD)
 484                 seqid = SEQID_BRRD;
 485         else
 486                 seqid = SEQID_RDEAR;
 487
 488         qspi_write32(priv->flags, &regs->ipcr,
 489                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 490
 491         /* Wait previous command complete */
 492         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 493                 ;
 494
 495         while (1) {
 496                 reg = qspi_read32(priv->flags, &regs->rbsr);
 497                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 498                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 499                         data = qspi_endian_xchg(data);
 500                         memcpy(rxbuf, &data, len);
 501                         qspi_write32(priv->flags, &regs->mcr,
 502                                      qspi_read32(priv->flags, &regs->mcr) |
 503                                      QSPI_MCR_CLR_RXF_MASK);
 504                         break;
 505                 }
 506         }
 507
 508         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 509 }
 510 #endif
 511
 512 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 513 {
 514         struct fsl_qspi_regs *regs = priv->regs;
 515         u32 mcr_reg, rbsr_reg, data, size;
 516         int i;
 517
 518         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 519         qspi_write32(priv->flags, &regs->mcr,
 520                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 521                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 522         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 523
 524         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 525
 526         qspi_write32(priv->flags, &regs->ipcr,
 527                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 528         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 529                 ;
 530
 531         i = 0;
 532         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 533                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 534                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 535                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 536                         data = qspi_endian_xchg(data);
 537                         size = (len < 4) ? len : 4;
 538                         memcpy(rxbuf, &data, size);
 539                         len -= size;
 540                         rxbuf++;
 541                         i++;
 542                 }
 543         }
 544
 545         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 546 }
 547
 548 /* If not use AHB read, read data from ip interface */
 549 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 550 {
 551         struct fsl_qspi_regs *regs = priv->regs;
 552         u32 mcr_reg, data;
 553         int i, size;
 554         u32 to_or_from;
 555         u32 seqid;
 556
 557         if (priv->cur_seqid == QSPI_CMD_RDAR)
 558                 seqid = SEQID_RDAR;
 559         else
 560                 seqid = SEQID_FAST_READ;
 561
 562         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 563         qspi_write32(priv->flags, &regs->mcr,
 564                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 565                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 566         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 567
 568         to_or_from = priv->sf_addr + priv->cur_amba_base;
 569
 570         while (len > 0) {
 571                 WATCHDOG_RESET();
 572
 573                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 574
 575                 size = (len > RX_BUFFER_SIZE) ?
 576                         RX_BUFFER_SIZE : len;
 577
 578                 qspi_write32(priv->flags, &regs->ipcr,
 579                              (seqid << QSPI_IPCR_SEQID_SHIFT) |
 580                              size);
 581                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 582                         ;
 583
 584                 to_or_from += size;
 585                 len -= size;
 586
 587                 i = 0;
 588                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 589                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 590                         data = qspi_endian_xchg(data);
 591                         if (size < 4)
 592                                 memcpy(rxbuf, &data, size);
 593                         else
 594                                 memcpy(rxbuf, &data, 4);
 595                         rxbuf++;
 596                         size -= 4;
 597                         i++;
 598                 }
 599                 qspi_write32(priv->flags, &regs->mcr,
 600                              qspi_read32(priv->flags, &regs->mcr) |
 601                              QSPI_MCR_CLR_RXF_MASK);
 602         }
 603
 604         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 605 }
 606
 607 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 608 {
 609         struct fsl_qspi_regs *regs = priv->regs;
 610         u32 mcr_reg, data, reg, status_reg, seqid;
 611         int i, size, tx_size;
 612         u32 to_or_from = 0;
 613
 614         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 615         qspi_write32(priv->flags, &regs->mcr,
 616                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 617                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 618         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 619
 620         status_reg = 0;
 621         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 622                 WATCHDOG_RESET();
 623
 624                 qspi_write32(priv->flags, &regs->ipcr,
 625                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 626                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 627                         ;
 628
 629                 qspi_write32(priv->flags, &regs->ipcr,
 630                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 631                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 632                         ;
 633
 634                 reg = qspi_read32(priv->flags, &regs->rbsr);
 635                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 636                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 637                         status_reg = qspi_endian_xchg(status_reg);
 638                 }
 639                 qspi_write32(priv->flags, &regs->mcr,
 640                              qspi_read32(priv->flags, &regs->mcr) |
 641                              QSPI_MCR_CLR_RXF_MASK);
 642         }
 643
 644         /* Default is page programming */
 645         seqid = SEQID_PP;
 646         if (priv->cur_seqid == QSPI_CMD_WRAR)
 647                 seqid = SEQID_WRAR;
 648 #ifdef CONFIG_SPI_FLASH_BAR
 649         if (priv->cur_seqid == QSPI_CMD_BRWR)
 650                 seqid = SEQID_BRWR;
 651         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 652                 seqid = SEQID_WREAR;
 653 #endif
 654
 655         to_or_from = priv->sf_addr + priv->cur_amba_base;
 656
 657         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 658
 659         tx_size = (len > TX_BUFFER_SIZE) ?
 660                 TX_BUFFER_SIZE : len;
 661
 662         size = tx_size / 4;
 663         for (i = 0; i < size; i++) {
 664                 memcpy(&data, txbuf, 4);
 665                 data = qspi_endian_xchg(data);
 666                 qspi_write32(priv->flags, &regs->tbdr, data);
 667                 txbuf += 4;
 668         }
 669
 670         size = tx_size % 4;
 671         if (size) {
 672                 data = 0;
 673                 memcpy(&data, txbuf, size);
 674                 data = qspi_endian_xchg(data);
 675                 qspi_write32(priv->flags, &regs->tbdr, data);
 676         }
 677
 678         qspi_write32(priv->flags, &regs->ipcr,
 679                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 680         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 681                 ;
 682
 683         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 684 }
 685
 686 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 687 {
 688         struct fsl_qspi_regs *regs = priv->regs;
 689         u32 mcr_reg, reg, data;
 690
 691         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 692         qspi_write32(priv->flags, &regs->mcr,
 693                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 694                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 695         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 696
 697         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 698
 699         qspi_write32(priv->flags, &regs->ipcr,
 700                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 701         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 702                 ;
 703
 704         while (1) {
 705                 reg = qspi_read32(priv->flags, &regs->rbsr);
 706                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 707                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 708                         data = qspi_endian_xchg(data);
 709                         memcpy(rxbuf, &data, len);
 710                         qspi_write32(priv->flags, &regs->mcr,
 711                                      qspi_read32(priv->flags, &regs->mcr) |
 712                                      QSPI_MCR_CLR_RXF_MASK);
 713                         break;
 714                 }
 715         }
 716
 717         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 718 }
 719
 720 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 721 {
 722         struct fsl_qspi_regs *regs = priv->regs;
 723         u32 mcr_reg;
 724         u32 to_or_from = 0;
 725
 726         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 727         qspi_write32(priv->flags, &regs->mcr,
 728                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 729                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 730         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 731
 732         to_or_from = priv->sf_addr + priv->cur_amba_base;
 733         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 734
 735         qspi_write32(priv->flags, &regs->ipcr,
 736                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 737         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 738                 ;
 739
 740         if (priv->cur_seqid == QSPI_CMD_SE) {
 741                 qspi_write32(priv->flags, &regs->ipcr,
 742                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 743         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 744                 qspi_write32(priv->flags, &regs->ipcr,
 745                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 746         }
 747         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 748                 ;
 749
 750         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 751 }
 752
 753 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 754                 const void *dout, void *din, unsigned long flags)
 755 {
 756         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 757         static u32 wr_sfaddr;
 758         u32 txbuf;
 759
 760         if (dout) {
 761                 if (flags & SPI_XFER_BEGIN) {
 762                         priv->cur_seqid = *(u8 *)dout;
 763                         memcpy(&txbuf, dout, 4);
 764                 }
 765
 766                 if (flags == SPI_XFER_END) {
 767                         priv->sf_addr = wr_sfaddr;
 768                         qspi_op_write(priv, (u8 *)dout, bytes);
 769                         return 0;
 770                 }
 771
 772                 if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
 773                     priv->cur_seqid == QSPI_CMD_RDAR) {
 774                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 775                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 776                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 777                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 778                         qspi_op_erase(priv);
 779                 } else if (priv->cur_seqid == QSPI_CMD_PP ||
 780                            priv->cur_seqid == QSPI_CMD_WRAR) {
 781                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 782                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 783                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 784 #ifdef CONFIG_SPI_FLASH_BAR
 785                         wr_sfaddr = 0;
 786 #endif
 787                 }
 788         }
 789
 790         if (din) {
 791                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 792 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 793                         qspi_ahb_read(priv, din, bytes);
 794 #else
 795                         qspi_op_read(priv, din, bytes);
 796 #endif
 797                 } else if (priv->cur_seqid == QSPI_CMD_RDAR) {
 798                         qspi_op_read(priv, din, bytes);
 799                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 800                         qspi_op_rdid(priv, din, bytes);
 801                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 802                         qspi_op_rdsr(priv, din, bytes);
 803 #ifdef CONFIG_SPI_FLASH_BAR
 804                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 805                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 806                         priv->sf_addr = 0;
 807                         qspi_op_rdbank(priv, din, bytes);
 808                 }
 809 #endif
 810         }
 811
 812 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 813         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 814             (priv->cur_seqid == QSPI_CMD_PP) ||
 815             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 816             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 817             (priv->cur_seqid == QSPI_CMD_BRWR))
 818                 qspi_ahb_invalid(priv);
 819 #endif
 820
 821         return 0;
 822 }
 823
 824 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 825 {
 826         u32 mcr_val;
 827
 828         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 829         if (disable)
 830                 mcr_val |= QSPI_MCR_MDIS_MASK;
 831         else
 832                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 833         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 834 }
 835
 836 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 837 {
 838         u32 smpr_val;
 839
 840         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 841         smpr_val &= ~clear_bits;
 842         smpr_val |= set_bits;
 843         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 844 }
 845 #ifndef CONFIG_DM_SPI
 846 static unsigned long spi_bases[] = {
 847         QSPI0_BASE_ADDR,
 848 #ifdef CONFIG_MX6SX
 849         QSPI1_BASE_ADDR,
 850 #endif
 851 };
 852
 853 static unsigned long amba_bases[] = {
 854         QSPI0_AMBA_BASE,
 855 #ifdef CONFIG_MX6SX
 856         QSPI1_AMBA_BASE,
 857 #endif
 858 };
 859
 860 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
 861 {
 862         return container_of(slave, struct fsl_qspi, slave);
 863 }
 864
 865 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 866                 unsigned int max_hz, unsigned int mode)
 867 {
 868         u32 mcr_val;
 869         struct fsl_qspi *qspi;
 870         struct fsl_qspi_regs *regs;
 871         u32 total_size;
 872
 873         if (bus >= ARRAY_SIZE(spi_bases))
 874                 return NULL;
 875
 876         if (cs >= FSL_QSPI_FLASH_NUM)
 877                 return NULL;
 878
 879         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 880         if (!qspi)
 881                 return NULL;
 882
 883 #ifdef CONFIG_SYS_FSL_QSPI_BE
 884         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 885 #endif
 886
 887         regs = (struct fsl_qspi_regs *)spi_bases[bus];
 888         qspi->priv.regs = regs;
 889         /*
 890          * According cs, use different amba_base to choose the
 891          * corresponding flash devices.
 892          *
 893          * If not, only one flash device is used even if passing
 894          * different cs using `sf probe`
 895          */
 896         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 897
 898         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 899
 900         mcr_val = qspi_read32(qspi->priv.flags, &regs->mcr);
 901         qspi_write32(qspi->priv.flags, &regs->mcr,
 902                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
 903                      (mcr_val & QSPI_MCR_END_CFD_MASK));
 904
 905         qspi_cfg_smpr(&qspi->priv,
 906                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 907                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 908
 909         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 910         /*
 911          * Any read access to non-implemented addresses will provide
 912          * undefined results.
 913          *
 914          * In case single die flash devices, TOP_ADDR_MEMA2 and
 915          * TOP_ADDR_MEMB2 should be initialized/programmed to
 916          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 917          * setting the size of these devices to 0.  This would ensure
 918          * that the complete memory map is assigned to only one flash device.
 919          */
 920         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
 921                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 922         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
 923                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 924         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
 925                      total_size | amba_bases[bus]);
 926         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
 927                      total_size | amba_bases[bus]);
 928
 929         qspi_set_lut(&qspi->priv);
 930
 931 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 932         qspi_init_ahb_read(&qspi->priv);
 933 #endif
 934
 935         qspi_module_disable(&qspi->priv, 0);
 936
 937         return &qspi->slave;
 938 }
 939
 940 void spi_free_slave(struct spi_slave *slave)
 941 {
 942         struct fsl_qspi *qspi = to_qspi_spi(slave);
 943
 944         free(qspi);
 945 }
 946
 947 int spi_claim_bus(struct spi_slave *slave)
 948 {
 949         return 0;
 950 }
 951
 952 void spi_release_bus(struct spi_slave *slave)
 953 {
 954         /* Nothing to do */
 955 }
 956
 957 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 958                 const void *dout, void *din, unsigned long flags)
 959 {
 960         struct fsl_qspi *qspi = to_qspi_spi(slave);
 961
 962         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
 963 }
 964
 965 void spi_init(void)
 966 {
 967         /* Nothing to do */
 968 }
 969 #else
 970 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 971 {
 972         struct spi_slave *slave = dev_get_parent_priv(dev);
 973
 974         slave->max_write_size = TX_BUFFER_SIZE;
 975
 976         return 0;
 977 }
 978
 979 static int fsl_qspi_probe(struct udevice *bus)
 980 {
 981         u32 mcr_val;
 982         u32 amba_size_per_chip;
 983         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 984         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 985         struct dm_spi_bus *dm_spi_bus;
 986         int i;
 987
 988         dm_spi_bus = bus->uclass_priv;
 989
 990         dm_spi_bus->max_hz = plat->speed_hz;
 991
 992         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 993         priv->flags = plat->flags;
 994
 995         priv->speed_hz = plat->speed_hz;
 996         /*
 997          * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
 998          * AMBA memory zone should be located on the 0~4GB space
 999          * even on a 64bits cpu.
1000          */
1001         priv->amba_base[0] = (u32)plat->amba_base;
1002         priv->amba_total_size = (u32)plat->amba_total_size;
1003         priv->flash_num = plat->flash_num;
1004         priv->num_chipselect = plat->num_chipselect;
1005
1006         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
1007         qspi_write32(priv->flags, &priv->regs->mcr,
1008                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
1009                      (mcr_val & QSPI_MCR_END_CFD_MASK));
1010
1011         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
1012                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
1013
1014         /*
1015          * Assign AMBA memory zone for every chipselect
1016          * QuadSPI has two channels, every channel has two chipselects.
1017          * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
1018          * into two parts and assign to every channel. This indicate that every
1019          * channel only has one valid chipselect.
1020          * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
1021          * into four parts and assign to every chipselect.
1022          * Every channel will has two valid chipselects.
1023          */
1024         amba_size_per_chip = priv->amba_total_size >>
1025                              (priv->num_chipselect >> 1);
1026         for (i = 1 ; i < priv->num_chipselect ; i++)
1027                 priv->amba_base[i] =
1028                         amba_size_per_chip + priv->amba_base[i - 1];
1029
1030         /*
1031          * Any read access to non-implemented addresses will provide
1032          * undefined results.
1033          *
1034          * In case single die flash devices, TOP_ADDR_MEMA2 and
1035          * TOP_ADDR_MEMB2 should be initialized/programmed to
1036          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
1037          * setting the size of these devices to 0.  This would ensure
1038          * that the complete memory map is assigned to only one flash device.
1039          */
1040         qspi_write32(priv->flags, &priv->regs->sfa1ad,
1041                      priv->amba_base[0] + amba_size_per_chip);
1042         switch (priv->num_chipselect) {
1043         case 1:
1044                 break;
1045         case 2:
1046                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1047                              priv->amba_base[1]);
1048                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1049                              priv->amba_base[1] + amba_size_per_chip);
1050                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1051                              priv->amba_base[1] + amba_size_per_chip);
1052                 break;
1053         case 4:
1054                 qspi_write32(priv->flags, &priv->regs->sfa2ad,
1055                              priv->amba_base[2]);
1056                 qspi_write32(priv->flags, &priv->regs->sfb1ad,
1057                              priv->amba_base[3]);
1058                 qspi_write32(priv->flags, &priv->regs->sfb2ad,
1059                              priv->amba_base[3] + amba_size_per_chip);
1060                 break;
1061         default:
1062                 debug("Error: Unsupported chipselect number %u!\n",
1063                       priv->num_chipselect);
1064                 qspi_module_disable(priv, 1);
1065                 return -EINVAL;
1066         }
1067
1068         qspi_set_lut(priv);
1069
1070 #ifdef CONFIG_SYS_FSL_QSPI_AHB
1071         qspi_init_ahb_read(priv);
1072 #endif
1073
1074         qspi_module_disable(priv, 0);
1075
1076         return 0;
1077 }
1078
1079 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
1080 {
1081         struct fdt_resource res_regs, res_mem;
1082         struct fsl_qspi_platdata *plat = bus->platdata;
1083         const void *blob = gd->fdt_blob;
1084         int node = dev_of_offset(bus);
1085         int ret, flash_num = 0, subnode;
1086
1087         if (fdtdec_get_bool(blob, node, "big-endian"))
1088                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
1089
1090         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1091                                      "QuadSPI", &res_regs);
1092         if (ret) {
1093                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
1094                 return -ENOMEM;
1095         }
1096         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
1097                                      "QuadSPI-memory", &res_mem);
1098         if (ret) {
1099                 debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
1100                 return -ENOMEM;
1101         }
1102
1103         /* Count flash numbers */
1104         fdt_for_each_subnode(subnode, blob, node)
1105                 ++flash_num;
1106
1107         if (flash_num == 0) {
1108                 debug("Error: Missing flashes!\n");
1109                 return -ENODEV;
1110         }
1111
1112         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1113                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1114         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1115                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1116
1117         plat->reg_base = res_regs.start;
1118         plat->amba_base = res_mem.start;
1119         plat->amba_total_size = res_mem.end - res_mem.start + 1;
1120         plat->flash_num = flash_num;
1121
1122         debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
1123               __func__,
1124               (u64)plat->reg_base,
1125               (u64)plat->amba_base,
1126               (u64)plat->amba_total_size,
1127               plat->speed_hz,
1128               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1129               );
1130
1131         return 0;
1132 }
1133
1134 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1135                 const void *dout, void *din, unsigned long flags)
1136 {
1137         struct fsl_qspi_priv *priv;
1138         struct udevice *bus;
1139
1140         bus = dev->parent;
1141         priv = dev_get_priv(bus);
1142
1143         return qspi_xfer(priv, bitlen, dout, din, flags);
1144 }
1145
1146 static int fsl_qspi_claim_bus(struct udevice *dev)
1147 {
1148         struct fsl_qspi_priv *priv;
1149         struct udevice *bus;
1150         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1151
1152         bus = dev->parent;
1153         priv = dev_get_priv(bus);
1154
1155         priv->cur_amba_base = priv->amba_base[slave_plat->cs];
1156
1157         qspi_module_disable(priv, 0);
1158
1159         return 0;
1160 }
1161
1162 static int fsl_qspi_release_bus(struct udevice *dev)
1163 {
1164         struct fsl_qspi_priv *priv;
1165         struct udevice *bus;
1166
1167         bus = dev->parent;
1168         priv = dev_get_priv(bus);
1169
1170         qspi_module_disable(priv, 1);
1171
1172         return 0;
1173 }
1174
1175 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1176 {
1177         /* Nothing to do */
1178         return 0;
1179 }
1180
1181 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1182 {
1183         /* Nothing to do */
1184         return 0;
1185 }
1186
1187 static const struct dm_spi_ops fsl_qspi_ops = {
1188         .claim_bus      = fsl_qspi_claim_bus,
1189         .release_bus    = fsl_qspi_release_bus,
1190         .xfer           = fsl_qspi_xfer,
1191         .set_speed      = fsl_qspi_set_speed,
1192         .set_mode       = fsl_qspi_set_mode,
1193 };
1194
1195 static const struct udevice_id fsl_qspi_ids[] = {
1196         { .compatible = "fsl,vf610-qspi" },
1197         { .compatible = "fsl,imx6sx-qspi" },
1198         { }
1199 };
1200
1201 U_BOOT_DRIVER(fsl_qspi) = {
1202         .name   = "fsl_qspi",
1203         .id     = UCLASS_SPI,
1204         .of_match = fsl_qspi_ids,
1205         .ops    = &fsl_qspi_ops,
1206         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1207         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1208         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1209         .probe  = fsl_qspi_probe,
1210         .child_pre_probe = fsl_qspi_child_pre_probe,
1211 };
1212 #endif