git.sur5r.net Git - u-boot/blob - drivers/spi/fsl_qspi.c

   1 /*
   2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale Quad Serial Peripheral Interface (QSPI) driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <malloc.h>
  11 #include <spi.h>
  12 #include <asm/io.h>
  13 #include <linux/sizes.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <watchdog.h>
  17 #include "fsl_qspi.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 #define RX_BUFFER_SIZE          0x80
  22 #ifdef CONFIG_MX6SX
  23 #define TX_BUFFER_SIZE          0x200
  24 #else
  25 #define TX_BUFFER_SIZE          0x40
  26 #endif
  27
  28 #define OFFSET_BITS_MASK        GENMASK(23, 0)
  29
  30 #define FLASH_STATUS_WEL        0x02
  31
  32 /* SEQID */
  33 #define SEQID_WREN              1
  34 #define SEQID_FAST_READ         2
  35 #define SEQID_RDSR              3
  36 #define SEQID_SE                4
  37 #define SEQID_CHIP_ERASE        5
  38 #define SEQID_PP                6
  39 #define SEQID_RDID              7
  40 #define SEQID_BE_4K             8
  41 #ifdef CONFIG_SPI_FLASH_BAR
  42 #define SEQID_BRRD              9
  43 #define SEQID_BRWR              10
  44 #define SEQID_RDEAR             11
  45 #define SEQID_WREAR             12
  46 #endif
  47
  48 /* QSPI CMD */
  49 #define QSPI_CMD_PP             0x02    /* Page program (up to 256 bytes) */
  50 #define QSPI_CMD_RDSR           0x05    /* Read status register */
  51 #define QSPI_CMD_WREN           0x06    /* Write enable */
  52 #define QSPI_CMD_FAST_READ      0x0b    /* Read data bytes (high frequency) */
  53 #define QSPI_CMD_BE_4K          0x20    /* 4K erase */
  54 #define QSPI_CMD_CHIP_ERASE     0xc7    /* Erase whole flash chip */
  55 #define QSPI_CMD_SE             0xd8    /* Sector erase (usually 64KiB) */
  56 #define QSPI_CMD_RDID           0x9f    /* Read JEDEC ID */
  57
  58 /* Used for Micron, winbond and Macronix flashes */
  59 #define QSPI_CMD_WREAR          0xc5    /* EAR register write */
  60 #define QSPI_CMD_RDEAR          0xc8    /* EAR reigster read */
  61
  62 /* Used for Spansion flashes only. */
  63 #define QSPI_CMD_BRRD           0x16    /* Bank register read */
  64 #define QSPI_CMD_BRWR           0x17    /* Bank register write */
  65
  66 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
  67 #define QSPI_CMD_FAST_READ_4B   0x0c    /* Read data bytes (high frequency) */
  68 #define QSPI_CMD_PP_4B          0x12    /* Page program (up to 256 bytes) */
  69 #define QSPI_CMD_SE_4B          0xdc    /* Sector erase (usually 64KiB) */
  70
  71 /* fsl_qspi_platdata flags */
  72 #define QSPI_FLAG_REGMAP_ENDIAN_BIG     BIT(0)
  73
  74 /* default SCK frequency, unit: HZ */
  75 #define FSL_QSPI_DEFAULT_SCK_FREQ       50000000
  76
  77 /* QSPI max chipselect signals number */
  78 #define FSL_QSPI_MAX_CHIPSELECT_NUM     4
  79
  80 #ifdef CONFIG_DM_SPI
  81 /**
  82  * struct fsl_qspi_platdata - platform data for Freescale QSPI
  83  *
  84  * @flags: Flags for QSPI QSPI_FLAG_...
  85  * @speed_hz: Default SCK frequency
  86  * @reg_base: Base address of QSPI registers
  87  * @amba_base: Base address of QSPI memory mapping
  88  * @amba_total_size: size of QSPI memory mapping
  89  * @flash_num: Number of active slave devices
  90  * @num_chipselect: Number of QSPI chipselect signals
  91  */
  92 struct fsl_qspi_platdata {
  93         u32 flags;
  94         u32 speed_hz;
  95         u32 reg_base;
  96         u32 amba_base;
  97         u32 amba_total_size;
  98         u32 flash_num;
  99         u32 num_chipselect;
 100 };
 101 #endif
 102
 103 /**
 104  * struct fsl_qspi_priv - private data for Freescale QSPI
 105  *
 106  * @flags: Flags for QSPI QSPI_FLAG_...
 107  * @bus_clk: QSPI input clk frequency
 108  * @speed_hz: Default SCK frequency
 109  * @cur_seqid: current LUT table sequence id
 110  * @sf_addr: flash access offset
 111  * @amba_base: Base address of QSPI memory mapping of every CS
 112  * @amba_total_size: size of QSPI memory mapping
 113  * @cur_amba_base: Base address of QSPI memory mapping of current CS
 114  * @flash_num: Number of active slave devices
 115  * @num_chipselect: Number of QSPI chipselect signals
 116  * @regs: Point to QSPI register structure for I/O access
 117  */
 118 struct fsl_qspi_priv {
 119         u32 flags;
 120         u32 bus_clk;
 121         u32 speed_hz;
 122         u32 cur_seqid;
 123         u32 sf_addr;
 124         u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
 125         u32 amba_total_size;
 126         u32 cur_amba_base;
 127         u32 flash_num;
 128         u32 num_chipselect;
 129         struct fsl_qspi_regs *regs;
 130 };
 131
 132 #ifndef CONFIG_DM_SPI
 133 struct fsl_qspi {
 134         struct spi_slave slave;
 135         struct fsl_qspi_priv priv;
 136 };
 137 #endif
 138
 139 static u32 qspi_read32(u32 flags, u32 *addr)
 140 {
 141         return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 142                 in_be32(addr) : in_le32(addr);
 143 }
 144
 145 static void qspi_write32(u32 flags, u32 *addr, u32 val)
 146 {
 147         flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
 148                 out_be32(addr, val) : out_le32(addr, val);
 149 }
 150
 151 /* QSPI support swapping the flash read/write data
 152  * in hardware for LS102xA, but not for VF610 */
 153 static inline u32 qspi_endian_xchg(u32 data)
 154 {
 155 #ifdef CONFIG_VF610
 156         return swab32(data);
 157 #else
 158         return data;
 159 #endif
 160 }
 161
 162 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 163 {
 164         struct fsl_qspi_regs *regs = priv->regs;
 165         u32 lut_base;
 166
 167         /* Unlock the LUT */
 168         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 169         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
 170
 171         /* Write Enable */
 172         lut_base = SEQID_WREN * 4;
 173         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
 174                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 175         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 176         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 177         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 178
 179         /* Fast Read */
 180         lut_base = SEQID_FAST_READ * 4;
 181 #ifdef CONFIG_SPI_FLASH_BAR
 182         qspi_write32(priv->flags, &regs->lut[lut_base],
 183                      OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 184                      INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 185                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 186 #else
 187         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 188                 qspi_write32(priv->flags, &regs->lut[lut_base],
 189                              OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
 190                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 191                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 192         else
 193                 qspi_write32(priv->flags, &regs->lut[lut_base],
 194                              OPRND0(QSPI_CMD_FAST_READ_4B) |
 195                              PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
 196                              OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
 197                              INSTR1(LUT_ADDR));
 198 #endif
 199         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 200                      OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
 201                      OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
 202                      INSTR1(LUT_READ));
 203         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 204         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 205
 206         /* Read Status */
 207         lut_base = SEQID_RDSR * 4;
 208         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
 209                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 210                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 211         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 212         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 213         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 214
 215         /* Erase a sector */
 216         lut_base = SEQID_SE * 4;
 217 #ifdef CONFIG_SPI_FLASH_BAR
 218         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
 219                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 220                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 221 #else
 222         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 223                 qspi_write32(priv->flags, &regs->lut[lut_base],
 224                              OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
 225                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 226                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 227         else
 228                 qspi_write32(priv->flags, &regs->lut[lut_base],
 229                              OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
 230                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 231                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 232 #endif
 233         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 234         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 235         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 236
 237         /* Erase the whole chip */
 238         lut_base = SEQID_CHIP_ERASE * 4;
 239         qspi_write32(priv->flags, &regs->lut[lut_base],
 240                      OPRND0(QSPI_CMD_CHIP_ERASE) |
 241                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
 242         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 243         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 244         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 245
 246         /* Page Program */
 247         lut_base = SEQID_PP * 4;
 248 #ifdef CONFIG_SPI_FLASH_BAR
 249         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
 250                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 251                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 252 #else
 253         if (FSL_QSPI_FLASH_SIZE  <= SZ_16M)
 254                 qspi_write32(priv->flags, &regs->lut[lut_base],
 255                              OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
 256                              INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 257                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 258         else
 259                 qspi_write32(priv->flags, &regs->lut[lut_base],
 260                              OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
 261                              INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
 262                              PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 263 #endif
 264 #ifdef CONFIG_MX6SX
 265         /*
 266          * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
 267          * So, Use IDATSZ in IPCR to determine the size and here set 0.
 268          */
 269         qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
 270                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 271 #else
 272         qspi_write32(priv->flags, &regs->lut[lut_base + 1],
 273                      OPRND0(TX_BUFFER_SIZE) |
 274                      PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 275 #endif
 276         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 277         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 278
 279         /* READ ID */
 280         lut_base = SEQID_RDID * 4;
 281         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
 282                 PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
 283                 PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 284         qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
 285         qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
 286         qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
 287
 288         /* SUB SECTOR 4K ERASE */
 289         lut_base = SEQID_BE_4K * 4;
 290         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
 291                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
 292                      PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 293
 294 #ifdef CONFIG_SPI_FLASH_BAR
 295         /*
 296          * BRRD BRWR RDEAR WREAR are all supported, because it is hard to
 297          * dynamically check whether to set BRRD BRWR or RDEAR WREAR during
 298          * initialization.
 299          */
 300         lut_base = SEQID_BRRD * 4;
 301         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
 302                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 303                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 304
 305         lut_base = SEQID_BRWR * 4;
 306         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
 307                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 308                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 309
 310         lut_base = SEQID_RDEAR * 4;
 311         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
 312                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 313                      PAD1(LUT_PAD1) | INSTR1(LUT_READ));
 314
 315         lut_base = SEQID_WREAR * 4;
 316         qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
 317                      PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 318                      PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 319 #endif
 320         /* Lock the LUT */
 321         qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 322         qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
 323 }
 324
 325 #if defined(CONFIG_SYS_FSL_QSPI_AHB)
 326 /*
 327  * If we have changed the content of the flash by writing or erasing,
 328  * we need to invalidate the AHB buffer. If we do not do so, we may read out
 329  * the wrong data. The spec tells us reset the AHB domain and Serial Flash
 330  * domain at the same time.
 331  */
 332 static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
 333 {
 334         struct fsl_qspi_regs *regs = priv->regs;
 335         u32 reg;
 336
 337         reg = qspi_read32(priv->flags, &regs->mcr);
 338         reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
 339         qspi_write32(priv->flags, &regs->mcr, reg);
 340
 341         /*
 342          * The minimum delay : 1 AHB + 2 SFCK clocks.
 343          * Delay 1 us is enough.
 344          */
 345         udelay(1);
 346
 347         reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
 348         qspi_write32(priv->flags, &regs->mcr, reg);
 349 }
 350
 351 /* Read out the data from the AHB buffer. */
 352 static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
 353 {
 354         struct fsl_qspi_regs *regs = priv->regs;
 355         u32 mcr_reg;
 356
 357         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 358
 359         qspi_write32(priv->flags, &regs->mcr,
 360                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 361                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 362
 363         /* Read out the data directly from the AHB buffer. */
 364         memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
 365
 366         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 367 }
 368
 369 static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
 370 {
 371         u32 reg, reg2;
 372         struct fsl_qspi_regs *regs = priv->regs;
 373
 374         reg = qspi_read32(priv->flags, &regs->mcr);
 375         /* Disable the module */
 376         qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
 377
 378         /* Set the Sampling Register for DDR */
 379         reg2 = qspi_read32(priv->flags, &regs->smpr);
 380         reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
 381         reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
 382         qspi_write32(priv->flags, &regs->smpr, reg2);
 383
 384         /* Enable the module again (enable the DDR too) */
 385         reg |= QSPI_MCR_DDR_EN_MASK;
 386         /* Enable bit 29 for imx6sx */
 387         reg |= BIT(29);
 388
 389         qspi_write32(priv->flags, &regs->mcr, reg);
 390 }
 391
 392 /*
 393  * There are two different ways to read out the data from the flash:
 394  *  the "IP Command Read" and the "AHB Command Read".
 395  *
 396  * The IC guy suggests we use the "AHB Command Read" which is faster
 397  * then the "IP Command Read". (What's more is that there is a bug in
 398  * the "IP Command Read" in the Vybrid.)
 399  *
 400  * After we set up the registers for the "AHB Command Read", we can use
 401  * the memcpy to read the data directly. A "missed" access to the buffer
 402  * causes the controller to clear the buffer, and use the sequence pointed
 403  * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
 404  */
 405 static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
 406 {
 407         struct fsl_qspi_regs *regs = priv->regs;
 408
 409         /* AHB configuration for access buffer 0/1/2 .*/
 410         qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
 411         qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
 412         qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
 413         qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
 414                      (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
 415
 416         /* We only use the buffer3 */
 417         qspi_write32(priv->flags, &regs->buf0ind, 0);
 418         qspi_write32(priv->flags, &regs->buf1ind, 0);
 419         qspi_write32(priv->flags, &regs->buf2ind, 0);
 420
 421         /*
 422          * Set the default lut sequence for AHB Read.
 423          * Parallel mode is disabled.
 424          */
 425         qspi_write32(priv->flags, &regs->bfgencr,
 426                      SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
 427
 428         /*Enable DDR Mode*/
 429         qspi_enable_ddr_mode(priv);
 430 }
 431 #endif
 432
 433 #ifdef CONFIG_SPI_FLASH_BAR
 434 /* Bank register read/write, EAR register read/write */
 435 static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
 436 {
 437         struct fsl_qspi_regs *regs = priv->regs;
 438         u32 reg, mcr_reg, data, seqid;
 439
 440         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 441         qspi_write32(priv->flags, &regs->mcr,
 442                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 443                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 444         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 445
 446         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 447
 448         if (priv->cur_seqid == QSPI_CMD_BRRD)
 449                 seqid = SEQID_BRRD;
 450         else
 451                 seqid = SEQID_RDEAR;
 452
 453         qspi_write32(priv->flags, &regs->ipcr,
 454                      (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
 455
 456         /* Wait previous command complete */
 457         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 458                 ;
 459
 460         while (1) {
 461                 reg = qspi_read32(priv->flags, &regs->rbsr);
 462                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 463                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 464                         data = qspi_endian_xchg(data);
 465                         memcpy(rxbuf, &data, len);
 466                         qspi_write32(priv->flags, &regs->mcr,
 467                                      qspi_read32(priv->flags, &regs->mcr) |
 468                                      QSPI_MCR_CLR_RXF_MASK);
 469                         break;
 470                 }
 471         }
 472
 473         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 474 }
 475 #endif
 476
 477 static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 478 {
 479         struct fsl_qspi_regs *regs = priv->regs;
 480         u32 mcr_reg, rbsr_reg, data, size;
 481         int i;
 482
 483         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 484         qspi_write32(priv->flags, &regs->mcr,
 485                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 486                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 487         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 488
 489         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 490
 491         qspi_write32(priv->flags, &regs->ipcr,
 492                      (SEQID_RDID << QSPI_IPCR_SEQID_SHIFT) | 0);
 493         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 494                 ;
 495
 496         i = 0;
 497         while ((RX_BUFFER_SIZE >= len) && (len > 0)) {
 498                 rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);
 499                 if (rbsr_reg & QSPI_RBSR_RDBFL_MASK) {
 500                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 501                         data = qspi_endian_xchg(data);
 502                         size = (len < 4) ? len : 4;
 503                         memcpy(rxbuf, &data, size);
 504                         len -= size;
 505                         rxbuf++;
 506                         i++;
 507                 }
 508         }
 509
 510         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 511 }
 512
 513 #ifndef CONFIG_SYS_FSL_QSPI_AHB
 514 /* If not use AHB read, read data from ip interface */
 515 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 516 {
 517         struct fsl_qspi_regs *regs = priv->regs;
 518         u32 mcr_reg, data;
 519         int i, size;
 520         u32 to_or_from;
 521
 522         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 523         qspi_write32(priv->flags, &regs->mcr,
 524                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 525                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 526         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 527
 528         to_or_from = priv->sf_addr + priv->cur_amba_base;
 529
 530         while (len > 0) {
 531                 WATCHDOG_RESET();
 532
 533                 qspi_write32(priv->flags, &regs->sfar, to_or_from);
 534
 535                 size = (len > RX_BUFFER_SIZE) ?
 536                         RX_BUFFER_SIZE : len;
 537
 538                 qspi_write32(priv->flags, &regs->ipcr,
 539                              (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
 540                              size);
 541                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 542                         ;
 543
 544                 to_or_from += size;
 545                 len -= size;
 546
 547                 i = 0;
 548                 while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 549                         data = qspi_read32(priv->flags, &regs->rbdr[i]);
 550                         data = qspi_endian_xchg(data);
 551                         memcpy(rxbuf, &data, 4);
 552                         rxbuf++;
 553                         size -= 4;
 554                         i++;
 555                 }
 556                 qspi_write32(priv->flags, &regs->mcr,
 557                              qspi_read32(priv->flags, &regs->mcr) |
 558                              QSPI_MCR_CLR_RXF_MASK);
 559         }
 560
 561         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 562 }
 563 #endif
 564
 565 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 566 {
 567         struct fsl_qspi_regs *regs = priv->regs;
 568         u32 mcr_reg, data, reg, status_reg, seqid;
 569         int i, size, tx_size;
 570         u32 to_or_from = 0;
 571
 572         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 573         qspi_write32(priv->flags, &regs->mcr,
 574                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 575                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 576         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 577
 578         status_reg = 0;
 579         while ((status_reg & FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
 580                 WATCHDOG_RESET();
 581
 582                 qspi_write32(priv->flags, &regs->ipcr,
 583                              (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 584                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 585                         ;
 586
 587                 qspi_write32(priv->flags, &regs->ipcr,
 588                              (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 1);
 589                 while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 590                         ;
 591
 592                 reg = qspi_read32(priv->flags, &regs->rbsr);
 593                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 594                         status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);
 595                         status_reg = qspi_endian_xchg(status_reg);
 596                 }
 597                 qspi_write32(priv->flags, &regs->mcr,
 598                              qspi_read32(priv->flags, &regs->mcr) |
 599                              QSPI_MCR_CLR_RXF_MASK);
 600         }
 601
 602         /* Default is page programming */
 603         seqid = SEQID_PP;
 604 #ifdef CONFIG_SPI_FLASH_BAR
 605         if (priv->cur_seqid == QSPI_CMD_BRWR)
 606                 seqid = SEQID_BRWR;
 607         else if (priv->cur_seqid == QSPI_CMD_WREAR)
 608                 seqid = SEQID_WREAR;
 609 #endif
 610
 611         to_or_from = priv->sf_addr + priv->cur_amba_base;
 612
 613         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 614
 615         tx_size = (len > TX_BUFFER_SIZE) ?
 616                 TX_BUFFER_SIZE : len;
 617
 618         size = tx_size / 4;
 619         for (i = 0; i < size; i++) {
 620                 memcpy(&data, txbuf, 4);
 621                 data = qspi_endian_xchg(data);
 622                 qspi_write32(priv->flags, &regs->tbdr, data);
 623                 txbuf += 4;
 624         }
 625
 626         size = tx_size % 4;
 627         if (size) {
 628                 data = 0;
 629                 memcpy(&data, txbuf, size);
 630                 data = qspi_endian_xchg(data);
 631                 qspi_write32(priv->flags, &regs->tbdr, data);
 632         }
 633
 634         qspi_write32(priv->flags, &regs->ipcr,
 635                      (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
 636         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 637                 ;
 638
 639         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 640 }
 641
 642 static void qspi_op_rdsr(struct fsl_qspi_priv *priv, void *rxbuf, u32 len)
 643 {
 644         struct fsl_qspi_regs *regs = priv->regs;
 645         u32 mcr_reg, reg, data;
 646
 647         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 648         qspi_write32(priv->flags, &regs->mcr,
 649                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 650                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 651         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 652
 653         qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
 654
 655         qspi_write32(priv->flags, &regs->ipcr,
 656                      (SEQID_RDSR << QSPI_IPCR_SEQID_SHIFT) | 0);
 657         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 658                 ;
 659
 660         while (1) {
 661                 reg = qspi_read32(priv->flags, &regs->rbsr);
 662                 if (reg & QSPI_RBSR_RDBFL_MASK) {
 663                         data = qspi_read32(priv->flags, &regs->rbdr[0]);
 664                         data = qspi_endian_xchg(data);
 665                         memcpy(rxbuf, &data, len);
 666                         qspi_write32(priv->flags, &regs->mcr,
 667                                      qspi_read32(priv->flags, &regs->mcr) |
 668                                      QSPI_MCR_CLR_RXF_MASK);
 669                         break;
 670                 }
 671         }
 672
 673         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 674 }
 675
 676 static void qspi_op_erase(struct fsl_qspi_priv *priv)
 677 {
 678         struct fsl_qspi_regs *regs = priv->regs;
 679         u32 mcr_reg;
 680         u32 to_or_from = 0;
 681
 682         mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 683         qspi_write32(priv->flags, &regs->mcr,
 684                      QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
 685                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
 686         qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
 687
 688         to_or_from = priv->sf_addr + priv->cur_amba_base;
 689         qspi_write32(priv->flags, &regs->sfar, to_or_from);
 690
 691         qspi_write32(priv->flags, &regs->ipcr,
 692                      (SEQID_WREN << QSPI_IPCR_SEQID_SHIFT) | 0);
 693         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 694                 ;
 695
 696         if (priv->cur_seqid == QSPI_CMD_SE) {
 697                 qspi_write32(priv->flags, &regs->ipcr,
 698                              (SEQID_SE << QSPI_IPCR_SEQID_SHIFT) | 0);
 699         } else if (priv->cur_seqid == QSPI_CMD_BE_4K) {
 700                 qspi_write32(priv->flags, &regs->ipcr,
 701                              (SEQID_BE_4K << QSPI_IPCR_SEQID_SHIFT) | 0);
 702         }
 703         while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 704                 ;
 705
 706         qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 707 }
 708
 709 int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 710                 const void *dout, void *din, unsigned long flags)
 711 {
 712         u32 bytes = DIV_ROUND_UP(bitlen, 8);
 713         static u32 wr_sfaddr;
 714         u32 txbuf;
 715
 716         if (dout) {
 717                 if (flags & SPI_XFER_BEGIN) {
 718                         priv->cur_seqid = *(u8 *)dout;
 719                         memcpy(&txbuf, dout, 4);
 720                 }
 721
 722                 if (flags == SPI_XFER_END) {
 723                         priv->sf_addr = wr_sfaddr;
 724                         qspi_op_write(priv, (u8 *)dout, bytes);
 725                         return 0;
 726                 }
 727
 728                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 729                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 730                 } else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 731                            (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 732                         priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 733                         qspi_op_erase(priv);
 734                 } else if (priv->cur_seqid == QSPI_CMD_PP) {
 735                         wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 736                 } else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 737                          (priv->cur_seqid == QSPI_CMD_WREAR)) {
 738 #ifdef CONFIG_SPI_FLASH_BAR
 739                         wr_sfaddr = 0;
 740 #endif
 741                 }
 742         }
 743
 744         if (din) {
 745                 if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
 746 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 747                         qspi_ahb_read(priv, din, bytes);
 748 #else
 749                         qspi_op_read(priv, din, bytes);
 750 #endif
 751                 } else if (priv->cur_seqid == QSPI_CMD_RDID)
 752                         qspi_op_rdid(priv, din, bytes);
 753                 else if (priv->cur_seqid == QSPI_CMD_RDSR)
 754                         qspi_op_rdsr(priv, din, bytes);
 755 #ifdef CONFIG_SPI_FLASH_BAR
 756                 else if ((priv->cur_seqid == QSPI_CMD_BRRD) ||
 757                          (priv->cur_seqid == QSPI_CMD_RDEAR)) {
 758                         priv->sf_addr = 0;
 759                         qspi_op_rdbank(priv, din, bytes);
 760                 }
 761 #endif
 762         }
 763
 764 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 765         if ((priv->cur_seqid == QSPI_CMD_SE) ||
 766             (priv->cur_seqid == QSPI_CMD_PP) ||
 767             (priv->cur_seqid == QSPI_CMD_BE_4K) ||
 768             (priv->cur_seqid == QSPI_CMD_WREAR) ||
 769             (priv->cur_seqid == QSPI_CMD_BRWR))
 770                 qspi_ahb_invalid(priv);
 771 #endif
 772
 773         return 0;
 774 }
 775
 776 void qspi_module_disable(struct fsl_qspi_priv *priv, u8 disable)
 777 {
 778         u32 mcr_val;
 779
 780         mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);
 781         if (disable)
 782                 mcr_val |= QSPI_MCR_MDIS_MASK;
 783         else
 784                 mcr_val &= ~QSPI_MCR_MDIS_MASK;
 785         qspi_write32(priv->flags, &priv->regs->mcr, mcr_val);
 786 }
 787
 788 void qspi_cfg_smpr(struct fsl_qspi_priv *priv, u32 clear_bits, u32 set_bits)
 789 {
 790         u32 smpr_val;
 791
 792         smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);
 793         smpr_val &= ~clear_bits;
 794         smpr_val |= set_bits;
 795         qspi_write32(priv->flags, &priv->regs->smpr, smpr_val);
 796 }
 797 #ifndef CONFIG_DM_SPI
 798 static unsigned long spi_bases[] = {
 799         QSPI0_BASE_ADDR,
 800 #ifdef CONFIG_MX6SX
 801         QSPI1_BASE_ADDR,
 802 #endif
 803 };
 804
 805 static unsigned long amba_bases[] = {
 806         QSPI0_AMBA_BASE,
 807 #ifdef CONFIG_MX6SX
 808         QSPI1_AMBA_BASE,
 809 #endif
 810 };
 811
 812 static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
 813 {
 814         return container_of(slave, struct fsl_qspi, slave);
 815 }
 816
 817 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 818                 unsigned int max_hz, unsigned int mode)
 819 {
 820         struct fsl_qspi *qspi;
 821         struct fsl_qspi_regs *regs;
 822         u32 total_size;
 823
 824         if (bus >= ARRAY_SIZE(spi_bases))
 825                 return NULL;
 826
 827         if (cs >= FSL_QSPI_FLASH_NUM)
 828                 return NULL;
 829
 830         qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
 831         if (!qspi)
 832                 return NULL;
 833
 834 #ifdef CONFIG_SYS_FSL_QSPI_BE
 835         qspi->priv.flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 836 #endif
 837
 838         regs = (struct fsl_qspi_regs *)spi_bases[bus];
 839         qspi->priv.regs = regs;
 840         /*
 841          * According cs, use different amba_base to choose the
 842          * corresponding flash devices.
 843          *
 844          * If not, only one flash device is used even if passing
 845          * different cs using `sf probe`
 846          */
 847         qspi->priv.cur_amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 848
 849         qspi->slave.max_write_size = TX_BUFFER_SIZE;
 850
 851         qspi_write32(qspi->priv.flags, &regs->mcr,
 852                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
 853
 854         qspi_cfg_smpr(&qspi->priv,
 855                       ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 856                       QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 857
 858         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 859         /*
 860          * Any read access to non-implemented addresses will provide
 861          * undefined results.
 862          *
 863          * In case single die flash devices, TOP_ADDR_MEMA2 and
 864          * TOP_ADDR_MEMB2 should be initialized/programmed to
 865          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 866          * setting the size of these devices to 0.  This would ensure
 867          * that the complete memory map is assigned to only one flash device.
 868          */
 869         qspi_write32(qspi->priv.flags, &regs->sfa1ad,
 870                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 871         qspi_write32(qspi->priv.flags, &regs->sfa2ad,
 872                      FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
 873         qspi_write32(qspi->priv.flags, &regs->sfb1ad,
 874                      total_size | amba_bases[bus]);
 875         qspi_write32(qspi->priv.flags, &regs->sfb2ad,
 876                      total_size | amba_bases[bus]);
 877
 878         qspi_set_lut(&qspi->priv);
 879
 880 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 881         qspi_init_ahb_read(&qspi->priv);
 882 #endif
 883
 884         qspi_module_disable(&qspi->priv, 0);
 885
 886         return &qspi->slave;
 887 }
 888
 889 void spi_free_slave(struct spi_slave *slave)
 890 {
 891         struct fsl_qspi *qspi = to_qspi_spi(slave);
 892
 893         free(qspi);
 894 }
 895
 896 int spi_claim_bus(struct spi_slave *slave)
 897 {
 898         return 0;
 899 }
 900
 901 void spi_release_bus(struct spi_slave *slave)
 902 {
 903         /* Nothing to do */
 904 }
 905
 906 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 907                 const void *dout, void *din, unsigned long flags)
 908 {
 909         struct fsl_qspi *qspi = to_qspi_spi(slave);
 910
 911         return qspi_xfer(&qspi->priv, bitlen, dout, din, flags);
 912 }
 913
 914 void spi_init(void)
 915 {
 916         /* Nothing to do */
 917 }
 918 #else
 919 static int fsl_qspi_child_pre_probe(struct udevice *dev)
 920 {
 921         struct spi_slave *slave = dev_get_parent_priv(dev);
 922
 923         slave->max_write_size = TX_BUFFER_SIZE;
 924
 925         return 0;
 926 }
 927
 928 static int fsl_qspi_probe(struct udevice *bus)
 929 {
 930         u32 total_size;
 931         struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 932         struct fsl_qspi_priv *priv = dev_get_priv(bus);
 933         struct dm_spi_bus *dm_spi_bus;
 934
 935         dm_spi_bus = bus->uclass_priv;
 936
 937         dm_spi_bus->max_hz = plat->speed_hz;
 938
 939         priv->regs = (struct fsl_qspi_regs *)(uintptr_t)plat->reg_base;
 940         priv->flags = plat->flags;
 941
 942         priv->speed_hz = plat->speed_hz;
 943         priv->amba_base[0] = plat->amba_base;
 944         priv->amba_total_size = plat->amba_total_size;
 945         priv->flash_num = plat->flash_num;
 946         priv->num_chipselect = plat->num_chipselect;
 947
 948         qspi_write32(priv->flags, &priv->regs->mcr,
 949                      QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
 950
 951         qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 952                 QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 953
 954         total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
 955         /*
 956          * Any read access to non-implemented addresses will provide
 957          * undefined results.
 958          *
 959          * In case single die flash devices, TOP_ADDR_MEMA2 and
 960          * TOP_ADDR_MEMB2 should be initialized/programmed to
 961          * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
 962          * setting the size of these devices to 0.  This would ensure
 963          * that the complete memory map is assigned to only one flash device.
 964          */
 965         qspi_write32(priv->flags, &priv->regs->sfa1ad,
 966                      FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
 967         qspi_write32(priv->flags, &priv->regs->sfa2ad,
 968                      FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
 969         qspi_write32(priv->flags, &priv->regs->sfb1ad,
 970                      total_size | priv->amba_base[0]);
 971         qspi_write32(priv->flags, &priv->regs->sfb2ad,
 972                      total_size | priv->amba_base[0]);
 973
 974         qspi_set_lut(priv);
 975
 976 #ifdef CONFIG_SYS_FSL_QSPI_AHB
 977         qspi_init_ahb_read(priv);
 978 #endif
 979
 980         qspi_module_disable(priv, 0);
 981
 982         return 0;
 983 }
 984
 985 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 986 {
 987         struct reg_data {
 988                 u32 addr;
 989                 u32 size;
 990         } regs_data[2];
 991         struct fsl_qspi_platdata *plat = bus->platdata;
 992         const void *blob = gd->fdt_blob;
 993         int node = bus->of_offset;
 994         int ret, flash_num = 0, subnode;
 995
 996         if (fdtdec_get_bool(blob, node, "big-endian"))
 997                 plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 998
 999         ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
1000                                    sizeof(regs_data)/sizeof(u32));
1001         if (ret) {
1002                 debug("Error: can't get base addresses (ret = %d)!\n", ret);
1003                 return -ENOMEM;
1004         }
1005
1006         /* Count flash numbers */
1007         fdt_for_each_subnode(blob, subnode, node)
1008                 ++flash_num;
1009
1010         if (flash_num == 0) {
1011                 debug("Error: Missing flashes!\n");
1012                 return -ENODEV;
1013         }
1014
1015         plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
1016                                         FSL_QSPI_DEFAULT_SCK_FREQ);
1017         plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
1018                                               FSL_QSPI_MAX_CHIPSELECT_NUM);
1019
1020         plat->reg_base = regs_data[0].addr;
1021         plat->amba_base = regs_data[1].addr;
1022         plat->amba_total_size = regs_data[1].size;
1023         plat->flash_num = flash_num;
1024
1025         debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
1026               __func__,
1027               plat->reg_base,
1028               plat->amba_base,
1029               plat->amba_total_size,
1030               plat->speed_hz,
1031               plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
1032               );
1033
1034         return 0;
1035 }
1036
1037 static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen,
1038                 const void *dout, void *din, unsigned long flags)
1039 {
1040         struct fsl_qspi_priv *priv;
1041         struct udevice *bus;
1042
1043         bus = dev->parent;
1044         priv = dev_get_priv(bus);
1045
1046         return qspi_xfer(priv, bitlen, dout, din, flags);
1047 }
1048
1049 static int fsl_qspi_claim_bus(struct udevice *dev)
1050 {
1051         struct fsl_qspi_priv *priv;
1052         struct udevice *bus;
1053         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
1054
1055         bus = dev->parent;
1056         priv = dev_get_priv(bus);
1057
1058         priv->cur_amba_base =
1059                 priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
1060
1061         qspi_module_disable(priv, 0);
1062
1063         return 0;
1064 }
1065
1066 static int fsl_qspi_release_bus(struct udevice *dev)
1067 {
1068         struct fsl_qspi_priv *priv;
1069         struct udevice *bus;
1070
1071         bus = dev->parent;
1072         priv = dev_get_priv(bus);
1073
1074         qspi_module_disable(priv, 1);
1075
1076         return 0;
1077 }
1078
1079 static int fsl_qspi_set_speed(struct udevice *bus, uint speed)
1080 {
1081         /* Nothing to do */
1082         return 0;
1083 }
1084
1085 static int fsl_qspi_set_mode(struct udevice *bus, uint mode)
1086 {
1087         /* Nothing to do */
1088         return 0;
1089 }
1090
1091 static const struct dm_spi_ops fsl_qspi_ops = {
1092         .claim_bus      = fsl_qspi_claim_bus,
1093         .release_bus    = fsl_qspi_release_bus,
1094         .xfer           = fsl_qspi_xfer,
1095         .set_speed      = fsl_qspi_set_speed,
1096         .set_mode       = fsl_qspi_set_mode,
1097 };
1098
1099 static const struct udevice_id fsl_qspi_ids[] = {
1100         { .compatible = "fsl,vf610-qspi" },
1101         { .compatible = "fsl,imx6sx-qspi" },
1102         { }
1103 };
1104
1105 U_BOOT_DRIVER(fsl_qspi) = {
1106         .name   = "fsl_qspi",
1107         .id     = UCLASS_SPI,
1108         .of_match = fsl_qspi_ids,
1109         .ops    = &fsl_qspi_ops,
1110         .ofdata_to_platdata = fsl_qspi_ofdata_to_platdata,
1111         .platdata_auto_alloc_size = sizeof(struct fsl_qspi_platdata),
1112         .priv_auto_alloc_size = sizeof(struct fsl_qspi_priv),
1113         .probe  = fsl_qspi_probe,
1114         .child_pre_probe = fsl_qspi_child_pre_probe,
1115 };
1116 #endif