2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
20 #define SPI_OPCODE_WREN 0x06
21 #define SPI_OPCODE_FAST_READ 0x0b
23 struct ich_spi_platdata {
24 pci_dev_t dev; /* PCI device number */
25 int ich_version; /* Controller version, 7 or 9 */
26 bool use_sbase; /* Use SBASE instead of RCB */
34 void *base; /* Base of register set */
44 uint32_t *pr; /* only for ich9 */
45 int speed; /* pointer to speed control */
46 ulong max_speed; /* Maximum bus speed in MHz */
47 ulong cur_speed; /* Current bus speed */
48 struct spi_trans trans; /* current transaction in progress */
51 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
53 u8 value = readb(priv->base + reg);
55 debug("read %2.2x from %4.4x\n", value, reg);
60 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
62 u16 value = readw(priv->base + reg);
64 debug("read %4.4x from %4.4x\n", value, reg);
69 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
71 u32 value = readl(priv->base + reg);
73 debug("read %8.8x from %4.4x\n", value, reg);
78 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
80 writeb(value, priv->base + reg);
81 debug("wrote %2.2x to %4.4x\n", value, reg);
84 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
86 writew(value, priv->base + reg);
87 debug("wrote %4.4x to %4.4x\n", value, reg);
90 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
92 writel(value, priv->base + reg);
93 debug("wrote %8.8x to %4.4x\n", value, reg);
96 static void write_reg(struct ich_spi_priv *priv, const void *value,
97 int dest_reg, uint32_t size)
99 memcpy_toio(priv->base + dest_reg, value, size);
102 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
105 memcpy_fromio(value, priv->base + src_reg, size);
108 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
110 const uint32_t bbar_mask = 0x00ffff00;
111 uint32_t ichspi_bbar;
113 minaddr &= bbar_mask;
114 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
115 ichspi_bbar |= minaddr;
116 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
120 * Check if this device ID matches one of supported Intel PCH devices.
122 * Return the ICH version if there is a match, or zero otherwise.
124 static int get_ich_version(uint16_t device_id)
126 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
127 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
128 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
131 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
132 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
133 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
134 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
135 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
136 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)
142 /* @return 1 if the SPI flash supports the 33MHz speed */
143 static int ich9_can_do_33mhz(pci_dev_t dev)
147 /* Observe SPI Descriptor Component Section 0 */
148 pci_write_config_dword(dev, 0xb0, 0x1000);
150 /* Extract the Write/Erase SPI Frequency from descriptor */
151 pci_read_config_dword(dev, 0xb4, &fdod);
153 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
154 speed = (fdod >> 21) & 7;
159 static int ich_find_spi_controller(struct ich_spi_platdata *ich)
161 int last_bus = pci_last_busno();
164 if (last_bus == -1) {
165 debug("No PCI busses?\n");
169 for (bus = 0; bus <= last_bus; bus++) {
170 uint16_t vendor_id, device_id;
174 dev = PCI_BDF(bus, 31, 0);
175 pci_read_config_dword(dev, 0, &ids);
177 device_id = ids >> 16;
179 if (vendor_id == PCI_VENDOR_ID_INTEL) {
181 ich->ich_version = get_ich_version(device_id);
182 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
183 ich->use_sbase = true;
184 return ich->ich_version == 0 ? -ENODEV : 0;
188 debug("ICH SPI: No ICH found.\n");
192 static int ich_init_controller(struct ich_spi_platdata *plat,
193 struct ich_spi_priv *ctlr)
195 uint8_t *rcrb; /* Root Complex Register Block */
196 uint32_t rcba; /* Root Complex Base Address */
200 pci_read_config_dword(plat->dev, 0xf0, &rcba);
201 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
202 rcrb = (uint8_t *)(rcba & 0xffffc000);
204 /* SBASE is similar */
205 pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
206 sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
208 if (plat->ich_version == 7) {
209 struct ich7_spi_regs *ich7_spi;
211 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
212 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
213 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
214 ctlr->menubytes = sizeof(ich7_spi->opmenu);
215 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
216 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
217 ctlr->data = offsetof(struct ich7_spi_regs, spid);
218 ctlr->databytes = sizeof(ich7_spi->spid);
219 ctlr->status = offsetof(struct ich7_spi_regs, spis);
220 ctlr->control = offsetof(struct ich7_spi_regs, spic);
221 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
222 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
223 ctlr->base = ich7_spi;
224 } else if (plat->ich_version == 9) {
225 struct ich9_spi_regs *ich9_spi;
228 ich9_spi = (struct ich9_spi_regs *)sbase;
230 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
231 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
232 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
233 ctlr->menubytes = sizeof(ich9_spi->opmenu);
234 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
235 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
236 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
237 ctlr->databytes = sizeof(ich9_spi->fdata);
238 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
239 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
240 ctlr->speed = ctlr->control + 2;
241 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
242 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
243 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
244 ctlr->pr = &ich9_spi->pr[0];
245 ctlr->base = ich9_spi;
247 debug("ICH SPI: Unrecognised ICH version %d\n",
252 /* Work out the maximum speed we can support */
253 ctlr->max_speed = 20000000;
254 if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
255 ctlr->max_speed = 33000000;
256 debug("ICH SPI: Version %d detected at %p, speed %ld\n",
257 plat->ich_version, ctlr->base, ctlr->max_speed);
259 ich_set_bbar(ctlr, 0);
264 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
267 trans->bytesout -= bytes;
270 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
273 trans->bytesin -= bytes;
276 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
280 /* Try to guess spi type from read/write sizes. */
281 if (trans->bytesin == 0) {
282 if (trans->bytesout + data_bytes > 4)
284 * If bytesin = 0 and bytesout > 4, we presume this is
285 * a write data operation, which is accompanied by an
288 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
290 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
294 if (trans->bytesout == 1) { /* and bytesin is > 0 */
295 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
299 if (trans->bytesout == 4) /* and bytesin is > 0 */
300 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
302 /* Fast read command is called with 5 bytes instead of 4 */
303 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
304 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
309 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
312 uint8_t opmenu[ctlr->menubytes];
314 trans->opcode = trans->out[0];
315 spi_use_out(trans, 1);
316 if (!ctlr->ichspi_lock) {
317 /* The lock is off, so just use index 0. */
318 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
319 optypes = ich_readw(ctlr, ctlr->optype);
320 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
321 ich_writew(ctlr, optypes, ctlr->optype);
324 /* The lock is on. See if what we need is on the menu. */
326 uint16_t opcode_index;
328 /* Write Enable is handled as atomic prefix */
329 if (trans->opcode == SPI_OPCODE_WREN)
332 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
333 for (opcode_index = 0; opcode_index < ctlr->menubytes;
335 if (opmenu[opcode_index] == trans->opcode)
339 if (opcode_index == ctlr->menubytes) {
340 printf("ICH SPI: Opcode %x not found\n",
345 optypes = ich_readw(ctlr, ctlr->optype);
346 optype = (optypes >> (opcode_index * 2)) & 0x3;
347 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
348 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
349 trans->bytesout >= 3) {
350 /* We guessed wrong earlier. Fix it up. */
351 trans->type = optype;
353 if (optype != trans->type) {
354 printf("ICH SPI: Transaction doesn't fit type %d\n",
362 static int spi_setup_offset(struct spi_trans *trans)
364 /* Separate the SPI address and data. */
365 switch (trans->type) {
366 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
367 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
369 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
370 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
371 trans->offset = ((uint32_t)trans->out[0] << 16) |
372 ((uint32_t)trans->out[1] << 8) |
373 ((uint32_t)trans->out[2] << 0);
374 spi_use_out(trans, 3);
377 printf("Unrecognized SPI transaction type %#x\n", trans->type);
383 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
384 * below is true) or 0. In case the wait was for the bit(s) to set - write
385 * those bits back, which would cause resetting them.
387 * Return the last read status value on success or -1 on failure.
389 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
392 int timeout = 600000; /* This will result in 6s */
396 status = ich_readw(ctlr, ctlr->status);
397 if (wait_til_set ^ ((status & bitmask) == 0)) {
399 ich_writew(ctlr, status & bitmask,
407 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
412 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
413 const void *dout, void *din, unsigned long flags)
415 struct udevice *bus = dev_get_parent(dev);
416 struct ich_spi_platdata *plat = dev_get_platdata(bus);
417 struct ich_spi_priv *ctlr = dev_get_priv(bus);
419 int16_t opcode_index;
422 int bytes = bitlen / 8;
423 struct spi_trans *trans = &ctlr->trans;
424 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
428 /* We don't support writing partial bytes */
430 debug("ICH SPI: Accessing partial bytes not supported\n");
431 return -EPROTONOSUPPORT;
434 /* An empty end transaction can be ignored */
435 if (type == SPI_XFER_END && !dout && !din)
438 if (type & SPI_XFER_BEGIN)
439 memset(trans, '\0', sizeof(*trans));
441 /* Dp we need to come back later to finish it? */
442 if (dout && type == SPI_XFER_BEGIN) {
443 if (bytes > ICH_MAX_CMD_LEN) {
444 debug("ICH SPI: Command length limit exceeded\n");
447 memcpy(trans->cmd, dout, bytes);
448 trans->cmd_len = bytes;
449 debug("ICH SPI: Saved %d bytes\n", bytes);
454 * We process a 'middle' spi_xfer() call, which has no
455 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
456 * an end. We therefore repeat the command. This is because ICH
457 * seems to have no support for this, or because interest (in digging
458 * out the details and creating a special case in the code) is low.
460 if (trans->cmd_len) {
461 trans->out = trans->cmd;
462 trans->bytesout = trans->cmd_len;
464 debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
467 trans->bytesout = dout ? bytes : 0;
471 trans->bytesin = din ? bytes : 0;
473 /* There has to always at least be an opcode. */
474 if (!trans->bytesout) {
475 debug("ICH SPI: No opcode for transfer\n");
479 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
483 if (plat->ich_version == 7)
484 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
486 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
488 spi_setup_type(trans, using_cmd ? bytes : 0);
489 opcode_index = spi_setup_opcode(ctlr, trans);
490 if (opcode_index < 0)
492 with_address = spi_setup_offset(trans);
493 if (with_address < 0)
496 if (trans->opcode == SPI_OPCODE_WREN) {
498 * Treat Write Enable as Atomic Pre-Op if possible
499 * in order to prevent the Management Engine from
500 * issuing a transaction between WREN and DATA.
502 if (!ctlr->ichspi_lock)
503 ich_writew(ctlr, trans->opcode, ctlr->preop);
507 if (ctlr->speed && ctlr->max_speed >= 33000000) {
510 byte = ich_readb(ctlr, ctlr->speed);
511 if (ctlr->cur_speed >= 33000000)
512 byte |= SSFC_SCF_33MHZ;
514 byte &= ~SSFC_SCF_33MHZ;
515 ich_writeb(ctlr, byte, ctlr->speed);
518 /* See if we have used up the command data */
519 if (using_cmd && dout && bytes) {
521 trans->bytesout = bytes;
522 debug("ICH SPI: Moving to data, %d bytes\n", bytes);
525 /* Preset control fields */
526 control = ich_readw(ctlr, ctlr->control);
527 control &= ~SSFC_RESERVED;
528 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
530 /* Issue atomic preop cycle if needed */
531 if (ich_readw(ctlr, ctlr->preop))
534 if (!trans->bytesout && !trans->bytesin) {
535 /* SPI addresses are 24 bit only */
537 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
541 * This is a 'no data' command (like Write Enable), its
542 * bitesout size was 1, decremented to zero while executing
543 * spi_setup_opcode() above. Tell the chip to send the
546 ich_writew(ctlr, control, ctlr->control);
548 /* wait for the result */
549 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
553 if (status & SPIS_FCERR) {
554 debug("ICH SPI: Command transaction error\n");
562 * Check if this is a write command atempting to transfer more bytes
563 * than the controller can handle. Iterations for writes are not
564 * supported here because each SPI write command needs to be preceded
565 * and followed by other SPI commands, and this sequence is controlled
566 * by the SPI chip driver.
568 if (trans->bytesout > ctlr->databytes) {
569 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
574 * Read or write up to databytes bytes at a time until everything has
577 while (trans->bytesout || trans->bytesin) {
578 uint32_t data_length;
580 /* SPI addresses are 24 bit only */
581 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
584 data_length = min(trans->bytesout, ctlr->databytes);
586 data_length = min(trans->bytesin, ctlr->databytes);
588 /* Program data into FDATA0 to N */
589 if (trans->bytesout) {
590 write_reg(ctlr, trans->out, ctlr->data, data_length);
591 spi_use_out(trans, data_length);
593 trans->offset += data_length;
596 /* Add proper control fields' values */
597 control &= ~((ctlr->databytes - 1) << 8);
599 control |= (data_length - 1) << 8;
602 ich_writew(ctlr, control, ctlr->control);
604 /* Wait for Cycle Done Status or Flash Cycle Error. */
605 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
609 if (status & SPIS_FCERR) {
610 debug("ICH SPI: Data transaction error %x\n", status);
614 if (trans->bytesin) {
615 read_reg(ctlr, ctlr->data, trans->in, data_length);
616 spi_use_in(trans, data_length);
618 trans->offset += data_length;
622 /* Clear atomic preop now that xfer is done */
623 ich_writew(ctlr, 0, ctlr->preop);
629 * This uses the SPI controller from the Intel Cougar Point and Panther Point
630 * PCH to write-protect portions of the SPI flash until reboot. The changes
631 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
634 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
635 uint32_t length, int hint)
637 struct udevice *bus = dev->parent;
638 struct ich_spi_priv *ctlr = dev_get_priv(bus);
640 uint32_t upper_limit;
643 printf("%s: operation not supported on this chipset\n",
649 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
650 hint < 0 || hint > 4) {
651 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
652 lower_limit, length, hint);
656 upper_limit = lower_limit + length - 1;
659 * Determine bits to write, as follows:
660 * 31 Write-protection enable (includes erase operation)
662 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
663 * 15 Read-protection enable
665 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
667 tmplong = 0x80000000 |
668 ((upper_limit & 0x01fff000) << 4) |
669 ((lower_limit & 0x01fff000) >> 12);
671 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
673 ctlr->pr[hint] = tmplong;
678 static int ich_spi_probe(struct udevice *bus)
680 struct ich_spi_platdata *plat = dev_get_platdata(bus);
681 struct ich_spi_priv *priv = dev_get_priv(bus);
685 ret = ich_init_controller(plat, priv);
689 * Disable the BIOS write protect so write commands are allowed. On
690 * v9, deassert SMM BIOS Write Protect Disable.
692 if (plat->use_sbase) {
693 bios_cntl = ich_readb(priv, priv->bcr);
694 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
695 bios_cntl |= 1; /* Write Protect Disable (WPD) */
696 ich_writeb(priv, bios_cntl, priv->bcr);
698 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
699 if (plat->ich_version == 9)
700 bios_cntl &= ~(1 << 5);
701 pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
704 priv->cur_speed = priv->max_speed;
709 static int ich_spi_ofdata_to_platdata(struct udevice *bus)
711 struct ich_spi_platdata *plat = dev_get_platdata(bus);
714 ret = ich_find_spi_controller(plat);
721 static int ich_spi_set_speed(struct udevice *bus, uint speed)
723 struct ich_spi_priv *priv = dev_get_priv(bus);
725 priv->cur_speed = speed;
730 static int ich_spi_set_mode(struct udevice *bus, uint mode)
732 debug("%s: mode=%d\n", __func__, mode);
737 static int ich_spi_child_pre_probe(struct udevice *dev)
739 struct udevice *bus = dev_get_parent(dev);
740 struct ich_spi_platdata *plat = dev_get_platdata(bus);
741 struct ich_spi_priv *priv = dev_get_priv(bus);
742 struct spi_slave *slave = dev_get_parentdata(dev);
745 * Yes this controller can only write a small number of bytes at
746 * once! The limit is typically 64 bytes.
748 slave->max_write_size = priv->databytes;
750 * ICH 7 SPI controller only supports array read command
751 * and byte program command for SST flash
753 if (plat->ich_version == 7) {
754 slave->op_mode_rx = SPI_OPM_RX_AS;
755 slave->op_mode_tx = SPI_OPM_TX_BP;
761 static const struct dm_spi_ops ich_spi_ops = {
762 .xfer = ich_spi_xfer,
763 .set_speed = ich_spi_set_speed,
764 .set_mode = ich_spi_set_mode,
766 * cs_info is not needed, since we require all chip selects to be
767 * in the device tree explicitly
771 static const struct udevice_id ich_spi_ids[] = {
772 { .compatible = "intel,ich-spi" },
776 U_BOOT_DRIVER(ich_spi) = {
779 .of_match = ich_spi_ids,
781 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
782 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
783 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
784 .child_pre_probe = ich_spi_child_pre_probe,
785 .probe = ich_spi_probe,