2 * Copyright (c) 2011-12 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
6 * This file is derived from the flashrom project.
20 #define SPI_OPCODE_WREN 0x06
21 #define SPI_OPCODE_FAST_READ 0x0b
23 struct ich_spi_platdata {
24 pci_dev_t dev; /* PCI device number */
25 int ich_version; /* Controller version, 7 or 9 */
26 bool use_sbase; /* Use SBASE instead of RCB */
34 void *base; /* Base of register set */
44 uint32_t *pr; /* only for ich9 */
45 int speed; /* pointer to speed control */
46 ulong max_speed; /* Maximum bus speed in MHz */
47 ulong cur_speed; /* Current bus speed */
48 struct spi_trans trans; /* current transaction in progress */
51 static u8 ich_readb(struct ich_spi_priv *priv, int reg)
53 u8 value = readb(priv->base + reg);
55 debug("read %2.2x from %4.4x\n", value, reg);
60 static u16 ich_readw(struct ich_spi_priv *priv, int reg)
62 u16 value = readw(priv->base + reg);
64 debug("read %4.4x from %4.4x\n", value, reg);
69 static u32 ich_readl(struct ich_spi_priv *priv, int reg)
71 u32 value = readl(priv->base + reg);
73 debug("read %8.8x from %4.4x\n", value, reg);
78 static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
80 writeb(value, priv->base + reg);
81 debug("wrote %2.2x to %4.4x\n", value, reg);
84 static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
86 writew(value, priv->base + reg);
87 debug("wrote %4.4x to %4.4x\n", value, reg);
90 static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
92 writel(value, priv->base + reg);
93 debug("wrote %8.8x to %4.4x\n", value, reg);
96 static void write_reg(struct ich_spi_priv *priv, const void *value,
97 int dest_reg, uint32_t size)
99 memcpy_toio(priv->base + dest_reg, value, size);
102 static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
105 memcpy_fromio(value, priv->base + src_reg, size);
108 static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
110 const uint32_t bbar_mask = 0x00ffff00;
111 uint32_t ichspi_bbar;
113 minaddr &= bbar_mask;
114 ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
115 ichspi_bbar |= minaddr;
116 ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
120 * Check if this device ID matches one of supported Intel PCH devices.
122 * Return the ICH version if there is a match, or zero otherwise.
124 static int get_ich_version(uint16_t device_id)
126 if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
127 device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
128 device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
131 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
132 device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
133 (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
134 device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
135 device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
136 device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC ||
137 device_id == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LPC)
143 /* @return 1 if the SPI flash supports the 33MHz speed */
144 static int ich9_can_do_33mhz(pci_dev_t dev)
148 /* Observe SPI Descriptor Component Section 0 */
149 pci_write_config_dword(dev, 0xb0, 0x1000);
151 /* Extract the Write/Erase SPI Frequency from descriptor */
152 pci_read_config_dword(dev, 0xb4, &fdod);
154 /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
155 speed = (fdod >> 21) & 7;
160 static int ich_find_spi_controller(struct ich_spi_platdata *ich)
162 int last_bus = pci_last_busno();
165 if (last_bus == -1) {
166 debug("No PCI busses?\n");
170 for (bus = 0; bus <= last_bus; bus++) {
171 uint16_t vendor_id, device_id;
175 dev = PCI_BDF(bus, 31, 0);
176 pci_read_config_dword(dev, 0, &ids);
178 device_id = ids >> 16;
180 if (vendor_id == PCI_VENDOR_ID_INTEL) {
182 ich->ich_version = get_ich_version(device_id);
183 if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
184 ich->use_sbase = true;
185 return ich->ich_version == 0 ? -ENODEV : 0;
189 debug("ICH SPI: No ICH found.\n");
193 static int ich_init_controller(struct ich_spi_platdata *plat,
194 struct ich_spi_priv *ctlr)
196 uint8_t *rcrb; /* Root Complex Register Block */
197 uint32_t rcba; /* Root Complex Base Address */
201 pci_read_config_dword(plat->dev, 0xf0, &rcba);
202 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
203 rcrb = (uint8_t *)(rcba & 0xffffc000);
205 /* SBASE is similar */
206 pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
207 sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
209 if (plat->ich_version == 7) {
210 struct ich7_spi_regs *ich7_spi;
212 ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
213 ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
214 ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
215 ctlr->menubytes = sizeof(ich7_spi->opmenu);
216 ctlr->optype = offsetof(struct ich7_spi_regs, optype);
217 ctlr->addr = offsetof(struct ich7_spi_regs, spia);
218 ctlr->data = offsetof(struct ich7_spi_regs, spid);
219 ctlr->databytes = sizeof(ich7_spi->spid);
220 ctlr->status = offsetof(struct ich7_spi_regs, spis);
221 ctlr->control = offsetof(struct ich7_spi_regs, spic);
222 ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
223 ctlr->preop = offsetof(struct ich7_spi_regs, preop);
224 ctlr->base = ich7_spi;
225 } else if (plat->ich_version == 9) {
226 struct ich9_spi_regs *ich9_spi;
229 ich9_spi = (struct ich9_spi_regs *)sbase;
231 ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
232 ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
233 ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
234 ctlr->menubytes = sizeof(ich9_spi->opmenu);
235 ctlr->optype = offsetof(struct ich9_spi_regs, optype);
236 ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
237 ctlr->data = offsetof(struct ich9_spi_regs, fdata);
238 ctlr->databytes = sizeof(ich9_spi->fdata);
239 ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
240 ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
241 ctlr->speed = ctlr->control + 2;
242 ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
243 ctlr->preop = offsetof(struct ich9_spi_regs, preop);
244 ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
245 ctlr->pr = &ich9_spi->pr[0];
246 ctlr->base = ich9_spi;
248 debug("ICH SPI: Unrecognised ICH version %d\n",
253 /* Work out the maximum speed we can support */
254 ctlr->max_speed = 20000000;
255 if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
256 ctlr->max_speed = 33000000;
257 debug("ICH SPI: Version %d detected at %p, speed %ld\n",
258 plat->ich_version, ctlr->base, ctlr->max_speed);
260 ich_set_bbar(ctlr, 0);
265 static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
268 trans->bytesout -= bytes;
271 static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
274 trans->bytesin -= bytes;
277 static void spi_setup_type(struct spi_trans *trans, int data_bytes)
281 /* Try to guess spi type from read/write sizes. */
282 if (trans->bytesin == 0) {
283 if (trans->bytesout + data_bytes > 4)
285 * If bytesin = 0 and bytesout > 4, we presume this is
286 * a write data operation, which is accompanied by an
289 trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
291 trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
295 if (trans->bytesout == 1) { /* and bytesin is > 0 */
296 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
300 if (trans->bytesout == 4) /* and bytesin is > 0 */
301 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
303 /* Fast read command is called with 5 bytes instead of 4 */
304 if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
305 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
310 static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
313 uint8_t opmenu[ctlr->menubytes];
315 trans->opcode = trans->out[0];
316 spi_use_out(trans, 1);
317 if (!ctlr->ichspi_lock) {
318 /* The lock is off, so just use index 0. */
319 ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
320 optypes = ich_readw(ctlr, ctlr->optype);
321 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
322 ich_writew(ctlr, optypes, ctlr->optype);
325 /* The lock is on. See if what we need is on the menu. */
327 uint16_t opcode_index;
329 /* Write Enable is handled as atomic prefix */
330 if (trans->opcode == SPI_OPCODE_WREN)
333 read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
334 for (opcode_index = 0; opcode_index < ctlr->menubytes;
336 if (opmenu[opcode_index] == trans->opcode)
340 if (opcode_index == ctlr->menubytes) {
341 printf("ICH SPI: Opcode %x not found\n",
346 optypes = ich_readw(ctlr, ctlr->optype);
347 optype = (optypes >> (opcode_index * 2)) & 0x3;
348 if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
349 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
350 trans->bytesout >= 3) {
351 /* We guessed wrong earlier. Fix it up. */
352 trans->type = optype;
354 if (optype != trans->type) {
355 printf("ICH SPI: Transaction doesn't fit type %d\n",
363 static int spi_setup_offset(struct spi_trans *trans)
365 /* Separate the SPI address and data. */
366 switch (trans->type) {
367 case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
368 case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
370 case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
371 case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
372 trans->offset = ((uint32_t)trans->out[0] << 16) |
373 ((uint32_t)trans->out[1] << 8) |
374 ((uint32_t)trans->out[2] << 0);
375 spi_use_out(trans, 3);
378 printf("Unrecognized SPI transaction type %#x\n", trans->type);
384 * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
385 * below is true) or 0. In case the wait was for the bit(s) to set - write
386 * those bits back, which would cause resetting them.
388 * Return the last read status value on success or -1 on failure.
390 static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
393 int timeout = 600000; /* This will result in 6s */
397 status = ich_readw(ctlr, ctlr->status);
398 if (wait_til_set ^ ((status & bitmask) == 0)) {
400 ich_writew(ctlr, status & bitmask,
408 printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
413 static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
414 const void *dout, void *din, unsigned long flags)
416 struct udevice *bus = dev_get_parent(dev);
417 struct ich_spi_platdata *plat = dev_get_platdata(bus);
418 struct ich_spi_priv *ctlr = dev_get_priv(bus);
420 int16_t opcode_index;
423 int bytes = bitlen / 8;
424 struct spi_trans *trans = &ctlr->trans;
425 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
429 /* We don't support writing partial bytes */
431 debug("ICH SPI: Accessing partial bytes not supported\n");
432 return -EPROTONOSUPPORT;
435 /* An empty end transaction can be ignored */
436 if (type == SPI_XFER_END && !dout && !din)
439 if (type & SPI_XFER_BEGIN)
440 memset(trans, '\0', sizeof(*trans));
442 /* Dp we need to come back later to finish it? */
443 if (dout && type == SPI_XFER_BEGIN) {
444 if (bytes > ICH_MAX_CMD_LEN) {
445 debug("ICH SPI: Command length limit exceeded\n");
448 memcpy(trans->cmd, dout, bytes);
449 trans->cmd_len = bytes;
450 debug("ICH SPI: Saved %d bytes\n", bytes);
455 * We process a 'middle' spi_xfer() call, which has no
456 * SPI_XFER_BEGIN/END, as an independent transaction as if it had
457 * an end. We therefore repeat the command. This is because ICH
458 * seems to have no support for this, or because interest (in digging
459 * out the details and creating a special case in the code) is low.
461 if (trans->cmd_len) {
462 trans->out = trans->cmd;
463 trans->bytesout = trans->cmd_len;
465 debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
468 trans->bytesout = dout ? bytes : 0;
472 trans->bytesin = din ? bytes : 0;
474 /* There has to always at least be an opcode. */
475 if (!trans->bytesout) {
476 debug("ICH SPI: No opcode for transfer\n");
480 ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
484 if (plat->ich_version == 7)
485 ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
487 ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
489 spi_setup_type(trans, using_cmd ? bytes : 0);
490 opcode_index = spi_setup_opcode(ctlr, trans);
491 if (opcode_index < 0)
493 with_address = spi_setup_offset(trans);
494 if (with_address < 0)
497 if (trans->opcode == SPI_OPCODE_WREN) {
499 * Treat Write Enable as Atomic Pre-Op if possible
500 * in order to prevent the Management Engine from
501 * issuing a transaction between WREN and DATA.
503 if (!ctlr->ichspi_lock)
504 ich_writew(ctlr, trans->opcode, ctlr->preop);
508 if (ctlr->speed && ctlr->max_speed >= 33000000) {
511 byte = ich_readb(ctlr, ctlr->speed);
512 if (ctlr->cur_speed >= 33000000)
513 byte |= SSFC_SCF_33MHZ;
515 byte &= ~SSFC_SCF_33MHZ;
516 ich_writeb(ctlr, byte, ctlr->speed);
519 /* See if we have used up the command data */
520 if (using_cmd && dout && bytes) {
522 trans->bytesout = bytes;
523 debug("ICH SPI: Moving to data, %d bytes\n", bytes);
526 /* Preset control fields */
527 control = ich_readw(ctlr, ctlr->control);
528 control &= ~SSFC_RESERVED;
529 control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
531 /* Issue atomic preop cycle if needed */
532 if (ich_readw(ctlr, ctlr->preop))
535 if (!trans->bytesout && !trans->bytesin) {
536 /* SPI addresses are 24 bit only */
538 ich_writel(ctlr, trans->offset & 0x00FFFFFF,
542 * This is a 'no data' command (like Write Enable), its
543 * bitesout size was 1, decremented to zero while executing
544 * spi_setup_opcode() above. Tell the chip to send the
547 ich_writew(ctlr, control, ctlr->control);
549 /* wait for the result */
550 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
554 if (status & SPIS_FCERR) {
555 debug("ICH SPI: Command transaction error\n");
563 * Check if this is a write command atempting to transfer more bytes
564 * than the controller can handle. Iterations for writes are not
565 * supported here because each SPI write command needs to be preceded
566 * and followed by other SPI commands, and this sequence is controlled
567 * by the SPI chip driver.
569 if (trans->bytesout > ctlr->databytes) {
570 debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
575 * Read or write up to databytes bytes at a time until everything has
578 while (trans->bytesout || trans->bytesin) {
579 uint32_t data_length;
581 /* SPI addresses are 24 bit only */
582 ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
585 data_length = min(trans->bytesout, ctlr->databytes);
587 data_length = min(trans->bytesin, ctlr->databytes);
589 /* Program data into FDATA0 to N */
590 if (trans->bytesout) {
591 write_reg(ctlr, trans->out, ctlr->data, data_length);
592 spi_use_out(trans, data_length);
594 trans->offset += data_length;
597 /* Add proper control fields' values */
598 control &= ~((ctlr->databytes - 1) << 8);
600 control |= (data_length - 1) << 8;
603 ich_writew(ctlr, control, ctlr->control);
605 /* Wait for Cycle Done Status or Flash Cycle Error. */
606 status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
610 if (status & SPIS_FCERR) {
611 debug("ICH SPI: Data transaction error %x\n", status);
615 if (trans->bytesin) {
616 read_reg(ctlr, ctlr->data, trans->in, data_length);
617 spi_use_in(trans, data_length);
619 trans->offset += data_length;
623 /* Clear atomic preop now that xfer is done */
624 ich_writew(ctlr, 0, ctlr->preop);
630 * This uses the SPI controller from the Intel Cougar Point and Panther Point
631 * PCH to write-protect portions of the SPI flash until reboot. The changes
632 * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
635 int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
636 uint32_t length, int hint)
638 struct udevice *bus = dev->parent;
639 struct ich_spi_priv *ctlr = dev_get_priv(bus);
641 uint32_t upper_limit;
644 printf("%s: operation not supported on this chipset\n",
650 lower_limit > (0xFFFFFFFFUL - length) + 1 ||
651 hint < 0 || hint > 4) {
652 printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
653 lower_limit, length, hint);
657 upper_limit = lower_limit + length - 1;
660 * Determine bits to write, as follows:
661 * 31 Write-protection enable (includes erase operation)
663 * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
664 * 15 Read-protection enable
666 * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
668 tmplong = 0x80000000 |
669 ((upper_limit & 0x01fff000) << 4) |
670 ((lower_limit & 0x01fff000) >> 12);
672 printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
674 ctlr->pr[hint] = tmplong;
679 static int ich_spi_probe(struct udevice *bus)
681 struct ich_spi_platdata *plat = dev_get_platdata(bus);
682 struct ich_spi_priv *priv = dev_get_priv(bus);
686 ret = ich_init_controller(plat, priv);
690 * Disable the BIOS write protect so write commands are allowed. On
691 * v9, deassert SMM BIOS Write Protect Disable.
693 if (plat->use_sbase) {
694 bios_cntl = ich_readb(priv, priv->bcr);
695 bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
696 bios_cntl |= 1; /* Write Protect Disable (WPD) */
697 ich_writeb(priv, bios_cntl, priv->bcr);
699 pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
700 if (plat->ich_version == 9)
701 bios_cntl &= ~(1 << 5);
702 pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
705 priv->cur_speed = priv->max_speed;
710 static int ich_spi_ofdata_to_platdata(struct udevice *bus)
712 struct ich_spi_platdata *plat = dev_get_platdata(bus);
715 ret = ich_find_spi_controller(plat);
722 static int ich_spi_set_speed(struct udevice *bus, uint speed)
724 struct ich_spi_priv *priv = dev_get_priv(bus);
726 priv->cur_speed = speed;
731 static int ich_spi_set_mode(struct udevice *bus, uint mode)
733 debug("%s: mode=%d\n", __func__, mode);
738 static int ich_spi_child_pre_probe(struct udevice *dev)
740 struct udevice *bus = dev_get_parent(dev);
741 struct ich_spi_platdata *plat = dev_get_platdata(bus);
742 struct ich_spi_priv *priv = dev_get_priv(bus);
743 struct spi_slave *slave = dev_get_parentdata(dev);
746 * Yes this controller can only write a small number of bytes at
747 * once! The limit is typically 64 bytes.
749 slave->max_write_size = priv->databytes;
751 * ICH 7 SPI controller only supports array read command
752 * and byte program command for SST flash
754 if (plat->ich_version == 7) {
755 slave->op_mode_rx = SPI_OPM_RX_AS;
756 slave->op_mode_tx = SPI_OPM_TX_BP;
762 static const struct dm_spi_ops ich_spi_ops = {
763 .xfer = ich_spi_xfer,
764 .set_speed = ich_spi_set_speed,
765 .set_mode = ich_spi_set_mode,
767 * cs_info is not needed, since we require all chip selects to be
768 * in the device tree explicitly
772 static const struct udevice_id ich_spi_ids[] = {
773 { .compatible = "intel,ich-spi" },
777 U_BOOT_DRIVER(ich_spi) = {
780 .of_match = ich_spi_ids,
782 .ofdata_to_platdata = ich_spi_ofdata_to_platdata,
783 .platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
784 .priv_auto_alloc_size = sizeof(struct ich_spi_priv),
785 .child_pre_probe = ich_spi_child_pre_probe,
786 .probe = ich_spi_probe,