git.sur5r.net Git - u-boot/blob - drivers/spi/ich.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  *
   5  * This file is derived from the flashrom project.
   6  */
   7
   8 #ifndef _ICH_H_
   9 #define _ICH_H_
  10
  11 struct ich7_spi_regs {
  12         uint16_t spis;
  13         uint16_t spic;
  14         uint32_t spia;
  15         uint64_t spid[8];
  16         uint64_t _pad;
  17         uint32_t bbar;
  18         uint16_t preop;
  19         uint16_t optype;
  20         uint8_t opmenu[8];
  21 } __packed;
  22
  23 struct ich9_spi_regs {
  24         uint32_t bfpr;          /* 0x00 */
  25         uint16_t hsfs;
  26         uint16_t hsfc;
  27         uint32_t faddr;
  28         uint32_t _reserved0;
  29         uint32_t fdata[16];     /* 0x10 */
  30         uint32_t frap;          /* 0x50 */
  31         uint32_t freg[5];
  32         uint32_t _reserved1[3];
  33         uint32_t pr[5];         /* 0x74 */
  34         uint32_t _reserved2[2];
  35         uint8_t ssfs;           /* 0x90 */
  36         uint8_t ssfc[3];
  37         uint16_t preop;         /* 0x94 */
  38         uint16_t optype;
  39         uint8_t opmenu[8];      /* 0x98 */
  40         uint32_t bbar;
  41         uint8_t _reserved3[12];
  42         uint32_t fdoc;          /* 0xb0 */
  43         uint32_t fdod;
  44         uint8_t _reserved4[8];
  45         uint32_t afc;           /* 0xc0 */
  46         uint32_t lvscc;
  47         uint32_t uvscc;
  48         uint8_t _reserved5[4];
  49         uint32_t fpb;           /* 0xd0 */
  50         uint8_t _reserved6[28];
  51         uint32_t srdl;          /* 0xf0 */
  52         uint32_t srdc;
  53         uint32_t scs;
  54         uint32_t bcr;
  55 } __packed;
  56
  57 enum {
  58         SPIS_SCIP =             0x0001,
  59         SPIS_GRANT =            0x0002,
  60         SPIS_CDS =              0x0004,
  61         SPIS_FCERR =            0x0008,
  62         SSFS_AEL =              0x0010,
  63         SPIS_LOCK =             0x8000,
  64         SPIS_RESERVED_MASK =    0x7ff0,
  65         SSFS_RESERVED_MASK =    0x7fe2
  66 };
  67
  68 enum {
  69         SPIC_SCGO =             0x000002,
  70         SPIC_ACS =              0x000004,
  71         SPIC_SPOP =             0x000008,
  72         SPIC_DBC =              0x003f00,
  73         SPIC_DS =               0x004000,
  74         SPIC_SME =              0x008000,
  75         SSFC_SCF_MASK =         0x070000,
  76         SSFC_RESERVED =         0xf80000,
  77
  78         /* Mask for speed byte, biuts 23:16 of SSFC */
  79         SSFC_SCF_33MHZ  =       0x01,
  80 };
  81
  82 enum {
  83         HSFS_FDONE =            0x0001,
  84         HSFS_FCERR =            0x0002,
  85         HSFS_AEL =              0x0004,
  86         HSFS_BERASE_MASK =      0x0018,
  87         HSFS_BERASE_SHIFT =     3,
  88         HSFS_SCIP =             0x0020,
  89         HSFS_FDOPSS =           0x2000,
  90         HSFS_FDV =              0x4000,
  91         HSFS_FLOCKDN =          0x8000
  92 };
  93
  94 enum {
  95         HSFC_FGO =              0x0001,
  96         HSFC_FCYCLE_MASK =      0x0006,
  97         HSFC_FCYCLE_SHIFT =     1,
  98         HSFC_FDBC_MASK =        0x3f00,
  99         HSFC_FDBC_SHIFT =       8,
 100         HSFC_FSMIE =            0x8000
 101 };
 102
 103 enum {
 104         ICH_MAX_CMD_LEN         = 5,
 105 };
 106
 107 struct spi_trans {
 108         uint8_t cmd[ICH_MAX_CMD_LEN];
 109         int cmd_len;
 110         const uint8_t *out;
 111         uint32_t bytesout;
 112         uint8_t *in;
 113         uint32_t bytesin;
 114         uint8_t type;
 115         uint8_t opcode;
 116         uint32_t offset;
 117 };
 118
 119 #define SPI_OPCODE_WRSR         0x01
 120 #define SPI_OPCODE_PAGE_PROGRAM 0x02
 121 #define SPI_OPCODE_READ         0x03
 122 #define SPI_OPCODE_WRDIS        0x04
 123 #define SPI_OPCODE_RDSR         0x05
 124 #define SPI_OPCODE_WREN         0x06
 125 #define SPI_OPCODE_FAST_READ    0x0b
 126 #define SPI_OPCODE_ERASE_SECT   0x20
 127 #define SPI_OPCODE_READ_ID      0x9f
 128 #define SPI_OPCODE_ERASE_BLOCK  0xd8
 129
 130 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS         0
 131 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS        1
 132 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS       2
 133 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS      3
 134
 135 #define SPI_OPMENU_0    SPI_OPCODE_WRSR
 136 #define SPI_OPTYPE_0    SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
 137
 138 #define SPI_OPMENU_1    SPI_OPCODE_PAGE_PROGRAM
 139 #define SPI_OPTYPE_1    SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
 140
 141 #define SPI_OPMENU_2    SPI_OPCODE_READ
 142 #define SPI_OPTYPE_2    SPI_OPCODE_TYPE_READ_WITH_ADDRESS
 143
 144 #define SPI_OPMENU_3    SPI_OPCODE_RDSR
 145 #define SPI_OPTYPE_3    SPI_OPCODE_TYPE_READ_NO_ADDRESS
 146
 147 #define SPI_OPMENU_4    SPI_OPCODE_ERASE_SECT
 148 #define SPI_OPTYPE_4    SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
 149
 150 #define SPI_OPMENU_5    SPI_OPCODE_READ_ID
 151 #define SPI_OPTYPE_5    SPI_OPCODE_TYPE_READ_NO_ADDRESS
 152
 153 #define SPI_OPMENU_6    SPI_OPCODE_ERASE_BLOCK
 154 #define SPI_OPTYPE_6    SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
 155
 156 #define SPI_OPMENU_7    SPI_OPCODE_FAST_READ
 157 #define SPI_OPTYPE_7    SPI_OPCODE_TYPE_READ_WITH_ADDRESS
 158
 159 #define SPI_OPPREFIX    ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
 160 #define SPI_OPTYPE      ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
 161                          (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 <<  8) | \
 162                          (SPI_OPTYPE_3 <<  6) | (SPI_OPTYPE_2 <<  4) | \
 163                          (SPI_OPTYPE_1 <<  2) | (SPI_OPTYPE_0 <<  0))
 164 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
 165                           (SPI_OPMENU_5 <<  8) | (SPI_OPMENU_4 <<  0))
 166 #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
 167                           (SPI_OPMENU_1 <<  8) | (SPI_OPMENU_0 <<  0))
 168
 169 enum ich_version {
 170         ICHV_7,
 171         ICHV_9,
 172 };
 173
 174 struct ich_spi_platdata {
 175         enum ich_version ich_version;   /* Controller version, 7 or 9 */
 176         bool lockdown;                  /* lock down controller settings? */
 177 };
 178
 179 struct ich_spi_priv {
 180         int opmenu;
 181         int menubytes;
 182         void *base;             /* Base of register set */
 183         int preop;
 184         int optype;
 185         int addr;
 186         int data;
 187         unsigned databytes;
 188         int status;
 189         int control;
 190         int bbar;
 191         int bcr;
 192         uint32_t *pr;           /* only for ich9 */
 193         int speed;              /* pointer to speed control */
 194         ulong max_speed;        /* Maximum bus speed in MHz */
 195         ulong cur_speed;        /* Current bus speed */
 196         struct spi_trans trans; /* current transaction in progress */
 197 };
 198
 199 #endif /* _ICH_H_ */