2 * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
3 * With help from the common/soft_spi and cpu/mpc8260 drivers
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #if defined(CONFIG_MPC8XXX_SPI) && defined(CONFIG_HARD_SPI)
28 #include <asm/mpc8xxx_spi.h>
30 #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
31 #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
33 #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
34 #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
35 #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
36 #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
38 #define SPI_TIMEOUT 1000
42 volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
45 * SPI pins on the MPC83xx are not muxed, so all we do is initialize
48 spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
49 spi->mode = (spi->mode & 0xfff0ffff) | (1 << 16); /* Use SYSCLK / 8
51 spi->event = 0xffffffff; /* Clear all SPI events */
52 spi->mask = 0x00000000; /* Mask all SPI interrupts */
53 spi->com = 0; /* LST bit doesn't do anything, so disregard */
56 int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din)
58 volatile spi8xxx_t *spi = &((immap_t *) (CFG_IMMR))->spi;
59 unsigned int tmpdout, tmpdin, event;
60 int numBlks = bitlen / 32 + (bitlen % 32 ? 1 : 0);
62 unsigned char charSize = 32;
64 debug("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n",
65 (int)chipsel, *(uint *) dout, *(uint *) din, bitlen);
68 (*chipsel) (1); /* select the target chip */
70 spi->event = 0xffffffff; /* Clear all SPI events */
72 /* handle data in 32-bit chunks */
75 charSize = (bitlen >= 32 ? 32 : bitlen);
77 /* Shift data so it's msb-justified */
78 tmpdout = *(u32 *) dout >> (32 - charSize);
80 /* The LEN field of the SPMODE register is set as follows:
84 * 4 < len <= 16 len - 1
90 spi->mode = (spi->mode & 0xff0fffff) |
93 spi->mode = (spi->mode & 0xff0fffff) |
96 spi->mode = (spi->mode & 0xff0fffff);
97 /* Set up the next iteration if sending > 32 bits */
102 spi->tx = tmpdout; /* Write the data out */
103 debug("*** spi_xfer: ... %08x written\n", tmpdout);
106 * Wait for SPI transmit to get out
107 * or time out (1 second = 1000 ms)
108 * The NE event must be read and cleared first
110 for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
112 if (event & SPI_EV_NE) {
114 spi->event |= SPI_EV_NE;
117 *(u32 *) din = (tmpdin << (32 - charSize));
118 if (charSize == 32) {
119 /* Advance output buffer by 32 bits */
124 * Only bail when we've had both NE and NF events.
125 * This will cause timeouts on RO devices, so maybe
126 * in the future put an arbitrary delay after writing
127 * the device. Arbitrary delays suck, though...
129 if (isRead && (event & SPI_EV_NF))
132 if (tm >= SPI_TIMEOUT)
133 puts("*** spi_xfer: Time out during SPI transfer");
135 debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
139 (*chipsel) (0); /* deselect the target chip */
143 #endif /* CONFIG_HARD_SPI */