2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
17 /* i.MX27 has a completely wrong register layout and register definitions in the
18 * datasheet, the correct one is in the Freescale's Linux driver */
20 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
21 "See linux mxc_spi driver from Freescale for details."
24 static unsigned long spi_bases[] = {
25 MXC_SPI_BASE_ADDRESSES
28 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
33 #define OUT MXC_GPIO_DIRECTION_OUT
35 #define reg_read readl
36 #define reg_write(a, v) writel(v, a)
38 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
39 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
42 struct mxc_spi_slave {
43 struct spi_slave slave;
46 #if defined(MXC_ECSPI)
53 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
55 return container_of(slave, struct mxc_spi_slave, slave);
58 void spi_cs_activate(struct spi_slave *slave)
60 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
62 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
65 void spi_cs_deactivate(struct spi_slave *slave)
67 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
69 gpio_set_value(mxcs->gpio,
73 u32 get_cspi_div(u32 div)
77 for (i = 0; i < 8; i++) {
85 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
86 unsigned int max_hz, unsigned int mode)
88 unsigned int ctrl_reg;
92 clk_src = mxc_get_clock(MXC_CSPI_CLK);
94 div = DIV_ROUND_UP(clk_src, max_hz);
95 div = get_cspi_div(div);
97 debug("clk %d Hz, div %d, real clk %d Hz\n",
98 max_hz, div, clk_src / (4 << div));
100 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
101 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
102 MXC_CSPICTRL_DATARATE(div) |
110 ctrl_reg |= MXC_CSPICTRL_PHA;
112 ctrl_reg |= MXC_CSPICTRL_POL;
113 if (mode & SPI_CS_HIGH)
114 ctrl_reg |= MXC_CSPICTRL_SSPOL;
115 mxcs->ctrl_reg = ctrl_reg;
122 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
123 unsigned int max_hz, unsigned int mode)
125 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
126 s32 reg_ctrl, reg_config;
127 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
128 u32 pre_div = 0, post_div = 0;
129 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
132 printf("Error: desired clock is 0\n");
137 * Reset SPI and set all CSs to master mode, if toggling
138 * between slave and master mode we might see a glitch
141 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
142 reg_write(®s->ctrl, reg_ctrl);
143 reg_ctrl |= MXC_CSPICTRL_EN;
144 reg_write(®s->ctrl, reg_ctrl);
146 if (clk_src > max_hz) {
147 pre_div = (clk_src - 1) / max_hz;
148 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
149 post_div = fls(pre_div);
152 if (post_div >= 16) {
153 printf("Error: no divider for the freq: %d\n",
157 pre_div >>= post_div;
163 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
164 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
165 MXC_CSPICTRL_SELCHAN(cs);
166 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
167 MXC_CSPICTRL_PREDIV(pre_div);
168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
169 MXC_CSPICTRL_POSTDIV(post_div);
171 /* We need to disable SPI before changing registers */
172 reg_ctrl &= ~MXC_CSPICTRL_EN;
174 if (mode & SPI_CS_HIGH)
177 if (mode & SPI_CPOL) {
185 reg_config = reg_read(®s->cfg);
188 * Configuration register setup
189 * The MX51 supports different setup for each SS
191 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
192 (ss_pol << (cs + MXC_CSPICON_SSPOL));
193 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
194 (sclkpol << (cs + MXC_CSPICON_POL));
195 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
196 (sclkctl << (cs + MXC_CSPICON_CTL));
197 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
198 (sclkpha << (cs + MXC_CSPICON_PHA));
200 debug("reg_ctrl = 0x%x\n", reg_ctrl);
201 reg_write(®s->ctrl, reg_ctrl);
202 debug("reg_config = 0x%x\n", reg_config);
203 reg_write(®s->cfg, reg_config);
205 /* save config register and control register */
206 mxcs->ctrl_reg = reg_ctrl;
207 mxcs->cfg_reg = reg_config;
209 /* clear interrupt reg */
210 reg_write(®s->intr, 0);
211 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
217 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
218 const u8 *dout, u8 *din, unsigned long flags)
220 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
221 int nbytes = DIV_ROUND_UP(bitlen, 8);
223 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
227 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
228 __func__, bitlen, (u32)dout, (u32)din);
230 mxcs->ctrl_reg = (mxcs->ctrl_reg &
231 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
232 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
234 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
236 reg_write(®s->cfg, mxcs->cfg_reg);
239 /* Clear interrupt register */
240 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
243 * The SPI controller works only with words,
244 * check if less than a word is sent.
245 * Access to the FIFO is only 32 bit
249 cnt = (bitlen % 32) / 8;
251 for (i = 0; i < cnt; i++) {
252 data = (data << 8) | (*dout++ & 0xFF);
255 debug("Sending SPI 0x%x\n", data);
257 reg_write(®s->txdata, data);
266 /* Buffer is not 32-bit aligned */
267 if ((unsigned long)dout & 0x03) {
269 for (i = 0; i < 4; i++)
270 data = (data << 8) | (*dout++ & 0xFF);
273 data = cpu_to_be32(data);
277 debug("Sending SPI 0x%x\n", data);
278 reg_write(®s->txdata, data);
282 /* FIFO is written, now starts the transfer setting the XCH bit */
283 reg_write(®s->ctrl, mxcs->ctrl_reg |
284 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
287 status = reg_read(®s->stat);
288 /* Wait until the TC (Transfer completed) bit is set */
289 while ((status & MXC_CSPICTRL_TC) == 0) {
290 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
291 printf("spi_xchg_single: Timeout!\n");
294 status = reg_read(®s->stat);
297 /* Transfer completed, clear any pending request */
298 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
300 nbytes = DIV_ROUND_UP(bitlen, 8);
305 data = reg_read(®s->rxdata);
306 cnt = (bitlen % 32) / 8;
307 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
308 debug("SPI Rx unaligned: 0x%x\n", data);
310 memcpy(din, &data, cnt);
318 tmp = reg_read(®s->rxdata);
319 data = cpu_to_be32(tmp);
320 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
321 cnt = min(nbytes, sizeof(data));
323 memcpy(din, &data, cnt);
333 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
334 void *din, unsigned long flags)
336 int n_bytes = DIV_ROUND_UP(bitlen, 8);
340 u8 *p_outbuf = (u8 *)dout;
341 u8 *p_inbuf = (u8 *)din;
346 if (flags & SPI_XFER_BEGIN)
347 spi_cs_activate(slave);
349 while (n_bytes > 0) {
350 if (n_bytes < MAX_SPI_BYTES)
353 blk_size = MAX_SPI_BYTES;
355 n_bits = blk_size * 8;
357 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
362 p_outbuf += blk_size;
368 if (flags & SPI_XFER_END) {
369 spi_cs_deactivate(slave);
380 * Some SPI devices require active chip-select over multiple
381 * transactions, we achieve this using a GPIO. Still, the SPI
382 * controller has to be configured to use one of its own chipselects.
383 * To use this feature you have to implement board_spi_cs_gpio() to assign
384 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
385 * You must use some unused on this SPI controller cs between 0 and 3.
387 static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
388 unsigned int bus, unsigned int cs)
392 mxcs->gpio = board_spi_cs_gpio(bus, cs);
393 if (mxcs->gpio == -1)
396 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
398 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
405 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
406 unsigned int max_hz, unsigned int mode)
408 struct mxc_spi_slave *mxcs;
411 if (bus >= ARRAY_SIZE(spi_bases))
414 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
416 puts("mxc_spi: SPI Slave not allocated !\n");
420 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
422 ret = setup_cs_gpio(mxcs, bus, cs);
428 mxcs->base = spi_bases[bus];
430 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
432 printf("mxc_spi: cannot setup SPI controller\n");
439 void spi_free_slave(struct spi_slave *slave)
441 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
446 int spi_claim_bus(struct spi_slave *slave)
448 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
449 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
451 reg_write(®s->rxdata, 1);
453 reg_write(®s->ctrl, mxcs->ctrl_reg);
454 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
455 reg_write(®s->intr, 0);
460 void spi_release_bus(struct spi_slave *slave)
462 /* TODO: Shut the controller down */