2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
17 /* i.MX27 has a completely wrong register layout and register definitions in the
18 * datasheet, the correct one is in the Freescale's Linux driver */
20 #error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
21 "See linux mxc_spi driver from Freescale for details."
24 static unsigned long spi_bases[] = {
25 MXC_SPI_BASE_ADDRESSES
28 #define OUT MXC_GPIO_DIRECTION_OUT
30 #define reg_read readl
31 #define reg_write(a, v) writel(v, a)
33 #if !defined(CONFIG_SYS_SPI_MXC_WAIT)
34 #define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
37 struct mxc_spi_slave {
38 struct spi_slave slave;
41 #if defined(MXC_ECSPI)
48 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
50 return container_of(slave, struct mxc_spi_slave, slave);
53 void spi_cs_activate(struct spi_slave *slave)
55 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
57 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
60 void spi_cs_deactivate(struct spi_slave *slave)
62 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
64 gpio_set_value(mxcs->gpio,
68 u32 get_cspi_div(u32 div)
72 for (i = 0; i < 8; i++) {
80 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
81 unsigned int max_hz, unsigned int mode)
83 unsigned int ctrl_reg;
87 clk_src = mxc_get_clock(MXC_CSPI_CLK);
89 div = DIV_ROUND_UP(clk_src, max_hz);
90 div = get_cspi_div(div);
92 debug("clk %d Hz, div %d, real clk %d Hz\n",
93 max_hz, div, clk_src / (4 << div));
95 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
96 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
97 MXC_CSPICTRL_DATARATE(div) |
105 ctrl_reg |= MXC_CSPICTRL_PHA;
107 ctrl_reg |= MXC_CSPICTRL_POL;
108 if (mode & SPI_CS_HIGH)
109 ctrl_reg |= MXC_CSPICTRL_SSPOL;
110 mxcs->ctrl_reg = ctrl_reg;
117 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
118 unsigned int max_hz, unsigned int mode)
120 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
121 s32 reg_ctrl, reg_config;
122 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
123 u32 pre_div = 0, post_div = 0;
124 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
127 printf("Error: desired clock is 0\n");
132 * Reset SPI and set all CSs to master mode, if toggling
133 * between slave and master mode we might see a glitch
136 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
137 reg_write(®s->ctrl, reg_ctrl);
138 reg_ctrl |= MXC_CSPICTRL_EN;
139 reg_write(®s->ctrl, reg_ctrl);
141 if (clk_src > max_hz) {
142 pre_div = (clk_src - 1) / max_hz;
143 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
144 post_div = fls(pre_div);
147 if (post_div >= 16) {
148 printf("Error: no divider for the freq: %d\n",
152 pre_div >>= post_div;
158 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
159 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
160 MXC_CSPICTRL_SELCHAN(cs);
161 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
162 MXC_CSPICTRL_PREDIV(pre_div);
163 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
164 MXC_CSPICTRL_POSTDIV(post_div);
166 /* We need to disable SPI before changing registers */
167 reg_ctrl &= ~MXC_CSPICTRL_EN;
169 if (mode & SPI_CS_HIGH)
172 if (mode & SPI_CPOL) {
180 reg_config = reg_read(®s->cfg);
183 * Configuration register setup
184 * The MX51 supports different setup for each SS
186 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
187 (ss_pol << (cs + MXC_CSPICON_SSPOL));
188 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
189 (sclkpol << (cs + MXC_CSPICON_POL));
190 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
191 (sclkctl << (cs + MXC_CSPICON_CTL));
192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
193 (sclkpha << (cs + MXC_CSPICON_PHA));
195 debug("reg_ctrl = 0x%x\n", reg_ctrl);
196 reg_write(®s->ctrl, reg_ctrl);
197 debug("reg_config = 0x%x\n", reg_config);
198 reg_write(®s->cfg, reg_config);
200 /* save config register and control register */
201 mxcs->ctrl_reg = reg_ctrl;
202 mxcs->cfg_reg = reg_config;
204 /* clear interrupt reg */
205 reg_write(®s->intr, 0);
206 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
212 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
213 const u8 *dout, u8 *din, unsigned long flags)
215 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
216 int nbytes = DIV_ROUND_UP(bitlen, 8);
218 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
222 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
223 __func__, bitlen, (u32)dout, (u32)din);
225 mxcs->ctrl_reg = (mxcs->ctrl_reg &
226 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
227 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
229 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
231 reg_write(®s->cfg, mxcs->cfg_reg);
234 /* Clear interrupt register */
235 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
238 * The SPI controller works only with words,
239 * check if less than a word is sent.
240 * Access to the FIFO is only 32 bit
244 cnt = (bitlen % 32) / 8;
246 for (i = 0; i < cnt; i++) {
247 data = (data << 8) | (*dout++ & 0xFF);
250 debug("Sending SPI 0x%x\n", data);
252 reg_write(®s->txdata, data);
261 /* Buffer is not 32-bit aligned */
262 if ((unsigned long)dout & 0x03) {
264 for (i = 0; i < 4; i++)
265 data = (data << 8) | (*dout++ & 0xFF);
268 data = cpu_to_be32(data);
272 debug("Sending SPI 0x%x\n", data);
273 reg_write(®s->txdata, data);
277 /* FIFO is written, now starts the transfer setting the XCH bit */
278 reg_write(®s->ctrl, mxcs->ctrl_reg |
279 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
282 status = reg_read(®s->stat);
283 /* Wait until the TC (Transfer completed) bit is set */
284 while ((status & MXC_CSPICTRL_TC) == 0) {
285 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
286 printf("spi_xchg_single: Timeout!\n");
289 status = reg_read(®s->stat);
292 /* Transfer completed, clear any pending request */
293 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
295 nbytes = DIV_ROUND_UP(bitlen, 8);
300 data = reg_read(®s->rxdata);
301 cnt = (bitlen % 32) / 8;
302 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
303 debug("SPI Rx unaligned: 0x%x\n", data);
305 memcpy(din, &data, cnt);
313 tmp = reg_read(®s->rxdata);
314 data = cpu_to_be32(tmp);
315 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
316 cnt = min(nbytes, sizeof(data));
318 memcpy(din, &data, cnt);
328 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
329 void *din, unsigned long flags)
331 int n_bytes = DIV_ROUND_UP(bitlen, 8);
335 u8 *p_outbuf = (u8 *)dout;
336 u8 *p_inbuf = (u8 *)din;
341 if (flags & SPI_XFER_BEGIN)
342 spi_cs_activate(slave);
344 while (n_bytes > 0) {
345 if (n_bytes < MAX_SPI_BYTES)
348 blk_size = MAX_SPI_BYTES;
350 n_bits = blk_size * 8;
352 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
357 p_outbuf += blk_size;
363 if (flags & SPI_XFER_END) {
364 spi_cs_deactivate(slave);
374 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
379 * Some SPI devices require active chip-select over multiple
380 * transactions, we achieve this using a GPIO. Still, the SPI
381 * controller has to be configured to use one of its own chipselects.
382 * To use this feature you have to call spi_setup_slave() with
383 * cs = internal_cs | (gpio << 8), and you have to use some unused
384 * on this SPI controller cs between 0 and 3.
387 mxcs->gpio = cs >> 8;
389 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
391 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
401 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
402 unsigned int max_hz, unsigned int mode)
404 struct mxc_spi_slave *mxcs;
407 if (bus >= ARRAY_SIZE(spi_bases))
410 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
412 puts("mxc_spi: SPI Slave not allocated !\n");
416 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
418 ret = decode_cs(mxcs, cs);
426 mxcs->base = spi_bases[bus];
428 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
430 printf("mxc_spi: cannot setup SPI controller\n");
437 void spi_free_slave(struct spi_slave *slave)
439 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
444 int spi_claim_bus(struct spi_slave *slave)
446 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
447 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
449 reg_write(®s->rxdata, 1);
451 reg_write(®s->ctrl, mxcs->ctrl_reg);
452 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
453 reg_write(®s->intr, 0);
458 void spi_release_bus(struct spi_slave *slave)
460 /* TODO: Shut the controller down */