2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/errno.h>
27 #include <asm/arch/imx-regs.h>
28 #include <asm/arch/clock.h>
31 /* i.MX27 has a completely wrong register layout and register definitions in the
32 * datasheet, the correct one is in the Freescale's Linux driver */
34 #error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
35 "See linux mxc_spi driver from Freescale for details."
37 #elif defined(CONFIG_MX31)
39 #define MXC_CSPICTRL_EN (1 << 0)
40 #define MXC_CSPICTRL_MODE (1 << 1)
41 #define MXC_CSPICTRL_XCH (1 << 2)
42 #define MXC_CSPICTRL_SMC (1 << 3)
43 #define MXC_CSPICTRL_POL (1 << 4)
44 #define MXC_CSPICTRL_PHA (1 << 5)
45 #define MXC_CSPICTRL_SSCTL (1 << 6)
46 #define MXC_CSPICTRL_SSPOL (1 << 7)
47 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
48 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
49 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
50 #define MXC_CSPICTRL_TC (1 << 8)
51 #define MXC_CSPICTRL_RXOVF (1 << 6)
52 #define MXC_CSPICTRL_MAXBITS 0x1f
54 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
55 #define MAX_SPI_BYTES 4
57 static unsigned long spi_bases[] = {
63 #define mxc_get_clock(x) mx31_get_ipg_clk()
65 #elif defined(CONFIG_MX51)
67 #define MXC_CSPICTRL_EN (1 << 0)
68 #define MXC_CSPICTRL_MODE (1 << 1)
69 #define MXC_CSPICTRL_XCH (1 << 2)
70 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
71 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
72 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
73 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
74 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
75 #define MXC_CSPICTRL_MAXBITS 0xfff
76 #define MXC_CSPICTRL_TC (1 << 7)
77 #define MXC_CSPICTRL_RXOVF (1 << 6)
79 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
80 #define MAX_SPI_BYTES 32
82 /* Bit position inside CTRL register to be associated with SS */
83 #define MXC_CSPICTRL_CHAN 18
85 /* Bit position inside CON register to be associated with SS */
86 #define MXC_CSPICON_POL 4
87 #define MXC_CSPICON_PHA 0
88 #define MXC_CSPICON_SSPOL 12
90 static unsigned long spi_bases[] = {
96 #elif defined(CONFIG_MX35)
98 #define MXC_CSPICTRL_EN (1 << 0)
99 #define MXC_CSPICTRL_MODE (1 << 1)
100 #define MXC_CSPICTRL_XCH (1 << 2)
101 #define MXC_CSPICTRL_SMC (1 << 3)
102 #define MXC_CSPICTRL_POL (1 << 4)
103 #define MXC_CSPICTRL_PHA (1 << 5)
104 #define MXC_CSPICTRL_SSCTL (1 << 6)
105 #define MXC_CSPICTRL_SSPOL (1 << 7)
106 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
107 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
108 #define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
109 #define MXC_CSPICTRL_TC (1 << 7)
110 #define MXC_CSPICTRL_RXOVF (1 << 6)
111 #define MXC_CSPICTRL_MAXBITS 0xfff
113 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
114 #define MAX_SPI_BYTES 4
116 static unsigned long spi_bases[] = {
122 #error "Unsupported architecture"
125 #define OUT MXC_GPIO_DIRECTION_OUT
127 #define reg_read readl
128 #define reg_write(a, v) writel(v, a)
130 struct mxc_spi_slave {
131 struct spi_slave slave;
134 #if defined(CONFIG_MX51)
141 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
143 return container_of(slave, struct mxc_spi_slave, slave);
146 void spi_cs_activate(struct spi_slave *slave)
148 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
150 mxc_gpio_set(mxcs->gpio, mxcs->ss_pol);
153 void spi_cs_deactivate(struct spi_slave *slave)
155 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
157 mxc_gpio_set(mxcs->gpio,
161 u32 get_cspi_div(u32 div)
165 for (i = 0; i < 8; i++) {
172 #if defined(CONFIG_MX31) || defined(CONFIG_MX35)
173 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
174 unsigned int max_hz, unsigned int mode)
176 unsigned int ctrl_reg;
180 clk_src = mxc_get_clock(MXC_CSPI_CLK);
182 div = clk_src / max_hz;
183 div = get_cspi_div(div);
185 debug("clk %d Hz, div %d, real clk %d Hz\n",
186 max_hz, div, clk_src / (4 << div));
188 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
189 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
190 MXC_CSPICTRL_DATARATE(div) |
198 ctrl_reg |= MXC_CSPICTRL_PHA;
200 ctrl_reg |= MXC_CSPICTRL_POL;
201 if (mode & SPI_CS_HIGH)
202 ctrl_reg |= MXC_CSPICTRL_SSPOL;
203 mxcs->ctrl_reg = ctrl_reg;
209 #if defined(CONFIG_MX51)
210 static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
211 unsigned int max_hz, unsigned int mode)
213 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
214 s32 pre_div = 0, post_div = 0, i, reg_ctrl, reg_config;
215 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0;
216 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
219 printf("Error: desired clock is 0\n");
223 reg_ctrl = reg_read(®s->ctrl);
226 reg_write(®s->ctrl, 0);
227 reg_write(®s->ctrl, (reg_ctrl | 0x1));
230 * The following computation is taken directly from Freescale's code.
232 if (clk_src > max_hz) {
233 pre_div = clk_src / max_hz;
235 post_div = pre_div / 16;
239 for (i = 0; i < 16; i++) {
240 if ((1 << i) >= post_div)
244 printf("Error: no divider for the freq: %d\n",
252 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
253 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
254 MXC_CSPICTRL_SELCHAN(cs);
255 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
256 MXC_CSPICTRL_PREDIV(pre_div);
257 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
258 MXC_CSPICTRL_POSTDIV(post_div);
260 /* always set to master mode */
261 reg_ctrl |= 1 << (cs + 4);
263 /* We need to disable SPI before changing registers */
264 reg_ctrl &= ~MXC_CSPICTRL_EN;
266 if (mode & SPI_CS_HIGH)
275 reg_config = reg_read(®s->cfg);
278 * Configuration register setup
279 * The MX51 supports different setup for each SS
281 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
282 (ss_pol << (cs + MXC_CSPICON_SSPOL));
283 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
284 (sclkpol << (cs + MXC_CSPICON_POL));
285 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
286 (sclkpha << (cs + MXC_CSPICON_PHA));
288 debug("reg_ctrl = 0x%x\n", reg_ctrl);
289 reg_write(®s->ctrl, reg_ctrl);
290 debug("reg_config = 0x%x\n", reg_config);
291 reg_write(®s->cfg, reg_config);
293 /* save config register and control register */
294 mxcs->ctrl_reg = reg_ctrl;
295 mxcs->cfg_reg = reg_config;
297 /* clear interrupt reg */
298 reg_write(®s->intr, 0);
299 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
305 int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
306 const u8 *dout, u8 *din, unsigned long flags)
308 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
309 int nbytes = (bitlen + 7) / 8;
311 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
313 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
314 __func__, bitlen, (u32)dout, (u32)din);
316 mxcs->ctrl_reg = (mxcs->ctrl_reg &
317 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
318 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
320 reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
322 reg_write(®s->cfg, mxcs->cfg_reg);
325 /* Clear interrupt register */
326 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
329 * The SPI controller works only with words,
330 * check if less than a word is sent.
331 * Access to the FIFO is only 32 bit
335 cnt = (bitlen % 32) / 8;
337 for (i = 0; i < cnt; i++) {
338 data = (data << 8) | (*dout++ & 0xFF);
341 debug("Sending SPI 0x%x\n", data);
343 reg_write(®s->txdata, data);
352 /* Buffer is not 32-bit aligned */
353 if ((unsigned long)dout & 0x03) {
355 for (i = 0; i < 4; i++)
356 data = (data << 8) | (*dout++ & 0xFF);
359 data = cpu_to_be32(data);
363 debug("Sending SPI 0x%x\n", data);
364 reg_write(®s->txdata, data);
368 /* FIFO is written, now starts the transfer setting the XCH bit */
369 reg_write(®s->ctrl, mxcs->ctrl_reg |
370 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
372 /* Wait until the TC (Transfer completed) bit is set */
373 while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
376 /* Transfer completed, clear any pending request */
377 reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
379 nbytes = (bitlen + 7) / 8;
384 data = reg_read(®s->rxdata);
385 cnt = (bitlen % 32) / 8;
386 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
387 debug("SPI Rx unaligned: 0x%x\n", data);
389 memcpy(din, &data, cnt);
397 tmp = reg_read(®s->rxdata);
398 data = cpu_to_be32(tmp);
399 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
400 cnt = min(nbytes, sizeof(data));
402 memcpy(din, &data, cnt);
412 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
413 void *din, unsigned long flags)
415 int n_bytes = (bitlen + 7) / 8;
419 u8 *p_outbuf = (u8 *)dout;
420 u8 *p_inbuf = (u8 *)din;
425 if (flags & SPI_XFER_BEGIN)
426 spi_cs_activate(slave);
428 while (n_bytes > 0) {
429 if (n_bytes < MAX_SPI_BYTES)
432 blk_size = MAX_SPI_BYTES;
434 n_bits = blk_size * 8;
436 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
441 p_outbuf += blk_size;
447 if (flags & SPI_XFER_END) {
448 spi_cs_deactivate(slave);
458 static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
463 * Some SPI devices require active chip-select over multiple
464 * transactions, we achieve this using a GPIO. Still, the SPI
465 * controller has to be configured to use one of its own chipselects.
466 * To use this feature you have to call spi_setup_slave() with
467 * cs = internal_cs | (gpio << 8), and you have to use some unused
468 * on this SPI controller cs between 0 and 3.
471 mxcs->gpio = cs >> 8;
473 ret = mxc_gpio_direction(mxcs->gpio, OUT);
475 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
485 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
486 unsigned int max_hz, unsigned int mode)
488 struct mxc_spi_slave *mxcs;
491 if (bus >= ARRAY_SIZE(spi_bases))
494 mxcs = malloc(sizeof(struct mxc_spi_slave));
496 puts("mxc_spi: SPI Slave not allocated !\n");
500 ret = decode_cs(mxcs, cs);
508 mxcs->slave.bus = bus;
510 mxcs->base = spi_bases[bus];
511 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
513 ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
515 printf("mxc_spi: cannot setup SPI controller\n");
522 void spi_free_slave(struct spi_slave *slave)
524 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
529 int spi_claim_bus(struct spi_slave *slave)
531 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
532 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
534 reg_write(®s->rxdata, 1);
536 reg_write(®s->ctrl, mxcs->ctrl_reg);
537 reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
538 reg_write(®s->intr, 0);
543 void spi_release_bus(struct spi_slave *slave)
545 /* TODO: Shut the controller down */