2 * Register definitions for the OMAP3 McSPI Controller
4 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
6 * Parts taken from linux/drivers/spi/omap2_mcspi.c
7 * Copyright (C) 2005, 2006 Nokia Corporation
9 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
11 * SPDX-License-Identifier: GPL-2.0+
17 #if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
18 #define OMAP3_MCSPI1_BASE 0x48030100
19 #define OMAP3_MCSPI2_BASE 0x481A0100
21 #define OMAP3_MCSPI1_BASE 0x48098000
22 #define OMAP3_MCSPI2_BASE 0x4809A000
23 #define OMAP3_MCSPI3_BASE 0x480B8000
24 #define OMAP3_MCSPI4_BASE 0x480BA000
27 #define OMAP3_MCSPI_MAX_FREQ 48000000
29 /* OMAP3 McSPI registers */
30 struct mcspi_channel {
31 unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
32 unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
33 unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
34 unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
35 unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
39 unsigned char res1[0x10];
40 unsigned int sysconfig; /* 0x10 */
41 unsigned int sysstatus; /* 0x14 */
42 unsigned int irqstatus; /* 0x18 */
43 unsigned int irqenable; /* 0x1C */
44 unsigned int wakeupenable; /* 0x20 */
45 unsigned int syst; /* 0x24 */
46 unsigned int modulctrl; /* 0x28 */
47 struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
48 /* channel1: 0x40 - 0x50, bus 0 & 1 */
49 /* channel2: 0x54 - 0x64, bus 0 & 1 */
50 /* channel3: 0x68 - 0x78, bus 0 */
53 /* per-register bitmasks */
54 #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
55 #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
56 #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
57 #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
59 #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
61 #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
62 #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
63 #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
65 #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
66 #define OMAP3_MCSPI_CHCONF_POL BIT(1)
67 #define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
68 #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
69 #define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
70 #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
71 #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
72 #define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
73 #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
74 #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
75 #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
76 #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
77 #define OMAP3_MCSPI_CHCONF_IS BIT(18)
78 #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
79 #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
81 #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
82 #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
83 #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
85 #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
86 #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
88 #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
90 struct omap3_spi_slave {
91 struct spi_slave slave;
97 static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
99 return container_of(slave, struct omap3_spi_slave, slave);
102 int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp,
103 void *rxp, unsigned long flags);
104 int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp,
105 unsigned long flags);
106 int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp,
107 unsigned long flags);
109 #endif /* _OMAP3_SPI_H_ */