2 * Renesas RCar Gen3 RPC QSPI driver
4 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <dm/of_access.h>
14 #include <dt-structs.h>
16 #include <linux/errno.h>
20 #define RPC_CMNCR 0x0000 /* R/W */
21 #define RPC_CMNCR_MD BIT(31)
22 #define RPC_CMNCR_SFDE BIT(24)
23 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
24 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
25 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
27 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
28 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
29 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
30 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
31 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
32 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
34 #define RPC_CMNCR_CPHAT BIT(6)
35 #define RPC_CMNCR_CPHAR BIT(5)
36 #define RPC_CMNCR_SSLP BIT(4)
37 #define RPC_CMNCR_CPOL BIT(3)
38 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
40 #define RPC_SSLDR 0x0004 /* R/W */
41 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
42 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
43 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
45 #define RPC_DRCR 0x000C /* R/W */
46 #define RPC_DRCR_SSLN BIT(24)
47 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
48 #define RPC_DRCR_RCF BIT(9)
49 #define RPC_DRCR_RBE BIT(8)
50 #define RPC_DRCR_SSLE BIT(0)
52 #define RPC_DRCMR 0x0010 /* R/W */
53 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
54 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
56 #define RPC_DREAR 0x0014 /* R/W */
57 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
58 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
60 #define RPC_DROPR 0x0018 /* R/W */
61 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
62 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
63 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
64 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
66 #define RPC_DRENR 0x001C /* R/W */
67 #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
68 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
69 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
70 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
71 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
72 #define RPC_DRENR_DME BIT(15)
73 #define RPC_DRENR_CDE BIT(14)
74 #define RPC_DRENR_OCDE BIT(12)
75 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
76 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
78 #define RPC_SMCR 0x0020 /* R/W */
79 #define RPC_SMCR_SSLKP BIT(8)
80 #define RPC_SMCR_SPIRE BIT(2)
81 #define RPC_SMCR_SPIWE BIT(1)
82 #define RPC_SMCR_SPIE BIT(0)
84 #define RPC_SMCMR 0x0024 /* R/W */
85 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
86 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
88 #define RPC_SMADR 0x0028 /* R/W */
89 #define RPC_SMOPR 0x002C /* R/W */
90 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
91 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
92 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
93 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
95 #define RPC_SMENR 0x0030 /* R/W */
96 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
97 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
98 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
99 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
100 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
101 #define RPC_SMENR_DME BIT(15)
102 #define RPC_SMENR_CDE BIT(14)
103 #define RPC_SMENR_OCDE BIT(12)
104 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
105 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
106 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
108 #define RPC_SMRDR0 0x0038 /* R */
109 #define RPC_SMRDR1 0x003C /* R */
110 #define RPC_SMWDR0 0x0040 /* R/W */
111 #define RPC_SMWDR1 0x0044 /* R/W */
112 #define RPC_CMNSR 0x0048 /* R */
113 #define RPC_CMNSR_SSLF BIT(1)
114 #define RPC_CMNSR_TEND BIT(0)
116 #define RPC_DRDMCR 0x0058 /* R/W */
117 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
119 #define RPC_DRDRENR 0x005C /* R/W */
120 #define RPC_DRDRENR_HYPE (0x5 << 12)
121 #define RPC_DRDRENR_ADDRE BIT(8)
122 #define RPC_DRDRENR_OPDRE BIT(4)
123 #define RPC_DRDRENR_DRDRE BIT(0)
125 #define RPC_SMDMCR 0x0060 /* R/W */
126 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
128 #define RPC_SMDRENR 0x0064 /* R/W */
129 #define RPC_SMDRENR_HYPE (0x5 << 12)
130 #define RPC_SMDRENR_ADDRE BIT(8)
131 #define RPC_SMDRENR_OPDRE BIT(4)
132 #define RPC_SMDRENR_SPIDRE BIT(0)
134 #define RPC_PHYCNT 0x007C /* R/W */
135 #define RPC_PHYCNT_CAL BIT(31)
136 #define PRC_PHYCNT_OCTA_AA BIT(22)
137 #define PRC_PHYCNT_OCTA_SA BIT(23)
138 #define PRC_PHYCNT_EXDS BIT(21)
139 #define RPC_PHYCNT_OCT BIT(20)
140 #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15)
141 #define RPC_PHYCNT_WBUF2 BIT(4)
142 #define RPC_PHYCNT_WBUF BIT(2)
143 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
145 #define RPC_PHYINT 0x0088 /* R/W */
146 #define RPC_PHYINT_RSTEN BIT(18)
147 #define RPC_PHYINT_WPEN BIT(17)
148 #define RPC_PHYINT_INTEN BIT(16)
149 #define RPC_PHYINT_RST BIT(2)
150 #define RPC_PHYINT_WP BIT(1)
151 #define RPC_PHYINT_INT BIT(0)
153 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
154 #define RPC_WBUF_SIZE 0x100
156 DECLARE_GLOBAL_DATA_PTR;
158 struct rpc_spi_platdata {
161 s32 freq; /* Default clock freq, -1 for none */
164 struct rpc_spi_priv {
174 static int rpc_spi_wait_sslf(struct udevice *dev)
176 struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
178 return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_SSLF,
182 static int rpc_spi_wait_tend(struct udevice *dev)
184 struct rpc_spi_priv *priv = dev_get_priv(dev->parent);
186 return wait_for_bit_le32((void *)priv->regs + RPC_CMNSR, RPC_CMNSR_TEND,
190 static void rpc_spi_flush_read_cache(struct udevice *dev)
192 struct udevice *bus = dev->parent;
193 struct rpc_spi_priv *priv = dev_get_priv(bus);
195 /* Flush read cache */
196 writel(RPC_DRCR_SSLN | RPC_DRCR_RBURST(0x1f) |
197 RPC_DRCR_RCF | RPC_DRCR_RBE | RPC_DRCR_SSLE,
198 priv->regs + RPC_DRCR);
199 readl(priv->regs + RPC_DRCR);
203 static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
205 struct udevice *bus = dev->parent;
206 struct rpc_spi_priv *priv = dev_get_priv(bus);
209 * NOTE: The 0x260 are undocumented bits, but they must be set.
210 * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the
211 * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the
212 * RPC_PHYCNT_STRTIM shall be 6.
214 writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260,
215 priv->regs + RPC_PHYCNT);
216 writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE |
217 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0),
218 priv->regs + RPC_CMNCR);
220 writel(RPC_SSLDR_SPNDL(7) | RPC_SSLDR_SLNDL(7) |
221 RPC_SSLDR_SCKDL(7), priv->regs + RPC_SSLDR);
223 rpc_spi_flush_read_cache(dev);
228 static int rpc_spi_release_bus(struct udevice *dev)
230 struct udevice *bus = dev->parent;
231 struct rpc_spi_priv *priv = dev_get_priv(bus);
233 /* NOTE: The 0x260 are undocumented bits, but they must be set. */
234 writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT);
236 rpc_spi_flush_read_cache(dev);
241 static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen,
242 const void *dout, void *din, unsigned long flags)
244 struct udevice *bus = dev->parent;
245 struct rpc_spi_priv *priv = dev_get_priv(bus);
246 u32 wlen = dout ? (bitlen / 8) : 0;
247 u32 rlen = din ? (bitlen / 8) : 0;
248 u32 wloop = DIV_ROUND_UP(wlen, 4);
249 u32 smenr, smcr, offset;
252 if (!priv->cmdstarted) {
256 memcpy(priv->cmdcopy, dout, wlen);
259 /* Command transfer start */
260 priv->cmdstarted = true;
261 if (!(flags & SPI_XFER_END))
265 offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) |
266 (priv->cmdcopy[3] << 0);
270 if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) {
271 if (wlen && flags == SPI_XFER_END)
272 smenr = RPC_SMENR_SPIDE(0xf);
274 rpc_spi_claim_bus(dev, true);
276 writel(0, priv->regs + RPC_SMCR);
278 if (priv->cmdlen >= 1) { /* Command(1) */
279 writel(RPC_SMCMR_CMD(priv->cmdcopy[0]),
280 priv->regs + RPC_SMCMR);
281 smenr |= RPC_SMENR_CDE;
283 writel(0, priv->regs + RPC_SMCMR);
286 if (priv->cmdlen >= 4) { /* Address(3) */
287 writel(offset, priv->regs + RPC_SMADR);
288 smenr |= RPC_SMENR_ADE(7);
290 writel(0, priv->regs + RPC_SMADR);
293 if (priv->cmdlen >= 5) { /* Dummy(n) */
294 writel(8 * (priv->cmdlen - 4) - 1,
295 priv->regs + RPC_SMDMCR);
296 smenr |= RPC_SMENR_DME;
298 writel(0, priv->regs + RPC_SMDMCR);
301 writel(0, priv->regs + RPC_SMOPR);
303 writel(0, priv->regs + RPC_SMDRENR);
305 if (wlen && flags == SPI_XFER_END) {
306 u32 *datout = (u32 *)dout;
309 smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE;
311 smcr |= RPC_SMCR_SSLKP;
312 writel(smenr, priv->regs + RPC_SMENR);
313 writel(*datout, priv->regs + RPC_SMWDR0);
314 writel(smcr, priv->regs + RPC_SMCR);
315 ret = rpc_spi_wait_tend(dev);
319 smenr = RPC_SMENR_SPIDE(0xf);
322 ret = rpc_spi_wait_sslf(dev);
325 writel(smenr, priv->regs + RPC_SMENR);
326 writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR);
327 ret = rpc_spi_wait_tend(dev);
329 } else { /* Read data only, using DRx ext access */
330 rpc_spi_claim_bus(dev, false);
332 if (priv->cmdlen >= 1) { /* Command(1) */
333 writel(RPC_DRCMR_CMD(priv->cmdcopy[0]),
334 priv->regs + RPC_DRCMR);
335 smenr |= RPC_DRENR_CDE;
337 writel(0, priv->regs + RPC_DRCMR);
340 if (priv->cmdlen >= 4) /* Address(3) */
341 smenr |= RPC_DRENR_ADE(7);
343 if (priv->cmdlen >= 5) { /* Dummy(n) */
344 writel(8 * (priv->cmdlen - 4) - 1,
345 priv->regs + RPC_DRDMCR);
346 smenr |= RPC_DRENR_DME;
348 writel(0, priv->regs + RPC_DRDMCR);
351 writel(0, priv->regs + RPC_DROPR);
353 writel(smenr, priv->regs + RPC_DRENR);
356 memcpy_fromio(din, (void *)(priv->extr + offset), rlen);
358 readl(priv->extr); /* Dummy read */
362 priv->cmdstarted = false;
364 rpc_spi_release_bus(dev);
369 static int rpc_spi_set_speed(struct udevice *bus, uint speed)
371 /* This is a SPI NOR controller, do nothing. */
375 static int rpc_spi_set_mode(struct udevice *bus, uint mode)
377 /* This is a SPI NOR controller, do nothing. */
381 static int rpc_spi_bind(struct udevice *parent)
383 const void *fdt = gd->fdt_blob;
388 * Check if there are any SPI NOR child nodes, if so, bind as
389 * this controller will be operated in SPI mode.
391 dev_for_each_subnode(node, parent) {
392 off = ofnode_to_offset(node);
394 ret = fdt_node_check_compatible(fdt, off, "spi-flash");
398 ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
406 static int rpc_spi_probe(struct udevice *dev)
408 struct rpc_spi_platdata *plat = dev_get_platdata(dev);
409 struct rpc_spi_priv *priv = dev_get_priv(dev);
411 priv->regs = plat->regs;
412 priv->extr = plat->extr;
414 clk_enable(&priv->clk);
419 static int rpc_spi_ofdata_to_platdata(struct udevice *bus)
421 struct rpc_spi_platdata *plat = dev_get_platdata(bus);
422 struct rpc_spi_priv *priv = dev_get_priv(bus);
425 plat->regs = dev_read_addr_index(bus, 0);
426 plat->extr = dev_read_addr_index(bus, 1);
428 ret = clk_get_by_index(bus, 0, &priv->clk);
430 printf("%s: Could not get clock for %s: %d\n",
431 __func__, bus->name, ret);
435 plat->freq = dev_read_u32_default(bus, "spi-max-freq", 50000000);
440 static const struct dm_spi_ops rpc_spi_ops = {
441 .xfer = rpc_spi_xfer,
442 .set_speed = rpc_spi_set_speed,
443 .set_mode = rpc_spi_set_mode,
446 static const struct udevice_id rpc_spi_ids[] = {
447 { .compatible = "renesas,rpc-r8a7795" },
448 { .compatible = "renesas,rpc-r8a7796" },
449 { .compatible = "renesas,rpc-r8a77965" },
450 { .compatible = "renesas,rpc-r8a77970" },
451 { .compatible = "renesas,rpc-r8a77995" },
455 U_BOOT_DRIVER(rpc_spi) = {
458 .of_match = rpc_spi_ids,
460 .ofdata_to_platdata = rpc_spi_ofdata_to_platdata,
461 .platdata_auto_alloc_size = sizeof(struct rpc_spi_platdata),
462 .priv_auto_alloc_size = sizeof(struct rpc_spi_priv),
463 .bind = rpc_spi_bind,
464 .probe = rpc_spi_probe,