2 * spi driver for rockchip
4 * (C) Copyright 2015 Google, Inc
6 * (C) Copyright 2008-2013 Rockchip Electronics
7 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/errno.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/periph.h>
21 #include <dm/pinctrl.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 /* Change to 1 to output registers at the start of each transaction */
27 #define DEBUG_RK_SPI 0
29 struct rockchip_spi_platdata {
30 s32 frequency; /* Default clock frequency, -1 for none */
32 uint deactivate_delay_us; /* Delay to wait after deactivate */
33 uint activate_delay_us; /* Delay to wait after activate */
36 struct rockchip_spi_priv {
37 struct rockchip_spi *regs;
40 unsigned int max_freq;
42 ulong last_transaction_us; /* Time of last transaction end */
43 u8 bits_per_word; /* max 16 bits per word */
45 unsigned int speed_hz;
46 unsigned int last_speed_hz;
51 #define SPI_FIFO_DEPTH 32
53 static void rkspi_dump_regs(struct rockchip_spi *regs)
55 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
56 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
57 debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
58 debug("ser: \t\t0x%08x\n", readl(®s->ser));
59 debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
60 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
61 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
62 debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
63 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
64 debug("sr: \t\t0x%08x\n", readl(®s->sr));
65 debug("imr: \t\t0x%08x\n", readl(®s->imr));
66 debug("isr: \t\t0x%08x\n", readl(®s->isr));
67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
68 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
69 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
72 static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
74 writel(enable ? 1 : 0, ®s->enr);
77 static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
81 clk_div = clk_get_divisor(priv->input_rate, speed);
82 debug("spi speed %u, div %u\n", speed, clk_div);
84 writel(clk_div, &priv->regs->baudr);
85 priv->last_speed_hz = speed;
88 static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
93 while (readl(®s->sr) & SR_BUSY) {
94 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
95 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
103 static void spi_cs_activate(struct udevice *dev, uint cs)
105 struct udevice *bus = dev->parent;
106 struct rockchip_spi_platdata *plat = bus->platdata;
107 struct rockchip_spi_priv *priv = dev_get_priv(bus);
108 struct rockchip_spi *regs = priv->regs;
110 debug("activate cs%u\n", cs);
111 writel(1 << cs, ®s->ser);
112 if (plat->activate_delay_us)
113 udelay(plat->activate_delay_us);
116 static void spi_cs_deactivate(struct udevice *dev, uint cs)
118 struct udevice *bus = dev->parent;
119 struct rockchip_spi_platdata *plat = bus->platdata;
120 struct rockchip_spi_priv *priv = dev_get_priv(bus);
121 struct rockchip_spi *regs = priv->regs;
123 debug("deactivate cs%u\n", cs);
124 writel(0, ®s->ser);
126 /* Remember time of this transaction so we can honour the bus delay */
127 if (plat->deactivate_delay_us)
128 priv->last_transaction_us = timer_get_us();
131 static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
133 struct rockchip_spi_platdata *plat = bus->platdata;
134 struct rockchip_spi_priv *priv = dev_get_priv(bus);
135 const void *blob = gd->fdt_blob;
136 int node = bus->of_offset;
139 plat->base = dev_get_addr(bus);
141 ret = clk_get_by_index(bus, 0, &priv->clk);
143 debug("%s: Could not get clock for %s: %d\n", __func__,
149 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
151 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
152 "spi-deactivate-delay", 0);
153 plat->activate_delay_us = fdtdec_get_int(blob, node,
154 "spi-activate-delay", 0);
155 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
156 __func__, (uint)plat->base, plat->frequency,
157 plat->deactivate_delay_us);
162 static int rockchip_spi_probe(struct udevice *bus)
164 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
165 struct rockchip_spi_priv *priv = dev_get_priv(bus);
168 debug("%s: probe\n", __func__);
169 priv->regs = (struct rockchip_spi *)plat->base;
171 priv->last_transaction_us = timer_get_us();
172 priv->max_freq = plat->frequency;
175 * Use 99 MHz as our clock since it divides nicely into 594 MHz which
176 * is the assumed speed for CLK_GENERAL.
178 ret = clk_set_periph_rate(priv->clk, priv->clk_id, 99000000);
180 debug("%s: Failed to set clock: %d\n", __func__, ret);
183 priv->input_rate = ret;
184 debug("%s: rate = %u\n", __func__, priv->input_rate);
185 priv->bits_per_word = 8;
186 priv->tmode = TMOD_TR; /* Tx & Rx */
191 static int rockchip_spi_claim_bus(struct udevice *dev)
193 struct udevice *bus = dev->parent;
194 struct rockchip_spi_priv *priv = dev_get_priv(bus);
195 struct rockchip_spi *regs = priv->regs;
199 /* Disable the SPI hardware */
200 rkspi_enable_chip(regs, 0);
202 switch (priv->bits_per_word) {
206 spi_tf = HALF_WORD_OFF;
211 spi_tf = HALF_WORD_ON;
214 debug("%s: unsupported bits: %dbits\n", __func__,
215 priv->bits_per_word);
216 return -EPROTONOSUPPORT;
219 if (priv->speed_hz != priv->last_speed_hz)
220 rkspi_set_clk(priv, priv->speed_hz);
223 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
225 /* Data Frame Size */
226 ctrlr0 |= spi_dfs << DFS_SHIFT;
228 /* set SPI mode 0..3 */
229 if (priv->mode & SPI_CPOL)
230 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
231 if (priv->mode & SPI_CPHA)
232 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
234 /* Chip Select Mode */
235 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
237 /* SSN to Sclk_out delay */
238 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
240 /* Serial Endian Mode */
241 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
244 ctrlr0 |= FBM_MSB << FBM_SHIFT;
246 /* Byte and Halfword Transform */
247 ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
249 /* Rxd Sample Delay */
250 ctrlr0 |= 0 << RXDSD_SHIFT;
253 ctrlr0 |= FRF_SPI << FRF_SHIFT;
256 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT;
258 writel(ctrlr0, ®s->ctrlr0);
263 static int rockchip_spi_release_bus(struct udevice *dev)
265 struct udevice *bus = dev->parent;
266 struct rockchip_spi_priv *priv = dev_get_priv(bus);
268 rkspi_enable_chip(priv->regs, false);
273 static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
274 const void *dout, void *din, unsigned long flags)
276 struct udevice *bus = dev->parent;
277 struct rockchip_spi_priv *priv = dev_get_priv(bus);
278 struct rockchip_spi *regs = priv->regs;
279 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
280 int len = bitlen >> 3;
281 const u8 *out = dout;
286 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
289 rkspi_dump_regs(regs);
291 /* Assert CS before transfer */
292 if (flags & SPI_XFER_BEGIN)
293 spi_cs_activate(dev, slave_plat->cs);
296 int todo = min(len, 0xffff);
298 rkspi_enable_chip(regs, false);
299 writel(todo - 1, ®s->ctrlr1);
300 rkspi_enable_chip(regs, true);
304 while (toread || towrite) {
305 u32 status = readl(®s->sr);
307 if (towrite && !(status & SR_TF_FULL)) {
308 writel(out ? *out++ : 0, regs->txdr);
311 if (toread && !(status & SR_RF_EMPT)) {
312 u32 byte = readl(regs->rxdr);
319 ret = rkspi_wait_till_not_busy(regs);
325 /* Deassert CS after transfer */
326 if (flags & SPI_XFER_END)
327 spi_cs_deactivate(dev, slave_plat->cs);
329 rkspi_enable_chip(regs, false);
334 static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
336 struct rockchip_spi_priv *priv = dev_get_priv(bus);
338 if (speed > ROCKCHIP_SPI_MAX_RATE)
340 if (speed > priv->max_freq)
341 speed = priv->max_freq;
342 priv->speed_hz = speed;
347 static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
349 struct rockchip_spi_priv *priv = dev_get_priv(bus);
356 static const struct dm_spi_ops rockchip_spi_ops = {
357 .claim_bus = rockchip_spi_claim_bus,
358 .release_bus = rockchip_spi_release_bus,
359 .xfer = rockchip_spi_xfer,
360 .set_speed = rockchip_spi_set_speed,
361 .set_mode = rockchip_spi_set_mode,
363 * cs_info is not needed, since we require all chip selects to be
364 * in the device tree explicitly
368 static const struct udevice_id rockchip_spi_ids[] = {
369 { .compatible = "rockchip,rk3288-spi" },
373 U_BOOT_DRIVER(rockchip_spi) = {
374 .name = "rockchip_spi",
376 .of_match = rockchip_spi_ids,
377 .ops = &rockchip_spi_ops,
378 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
379 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
380 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
381 .probe = rockchip_spi_probe,