1 // SPDX-License-Identifier: GPL-2.0
3 * SH QSPI (Quad SPI) driver
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
14 #include <asm/arch/rmobile.h>
17 /* SH QSPI register bit masks <REG>_<BIT> */
18 #define SPCR_MSTR 0x08
20 #define SPSR_SPRFF 0x80
21 #define SPSR_SPTEF 0x20
22 #define SPPCR_IO3FV 0x04
23 #define SPPCR_IO2FV 0x02
24 #define SPPCR_IO1FV 0x01
25 #define SPBDCR_RXBC0 BIT(0)
26 #define SPCMD_SCKDEN BIT(15)
27 #define SPCMD_SLNDEN BIT(14)
28 #define SPCMD_SPNDEN BIT(13)
29 #define SPCMD_SSLKP BIT(7)
30 #define SPCMD_BRDV0 BIT(2)
31 #define SPCMD_INIT1 SPCMD_SCKDEN | SPCMD_SLNDEN | \
32 SPCMD_SPNDEN | SPCMD_SSLKP | \
34 #define SPCMD_INIT2 SPCMD_SPNDEN | SPCMD_SSLKP | \
36 #define SPBFCR_TXRST BIT(7)
37 #define SPBFCR_RXRST BIT(6)
38 #define SPBFCR_TXTRG 0x30
39 #define SPBFCR_RXTRG 0x07
41 /* SH QSPI register set */
69 struct sh_qspi_slave {
70 struct spi_slave slave;
71 struct sh_qspi_regs *regs;
74 static inline struct sh_qspi_slave *to_sh_qspi(struct spi_slave *slave)
76 return container_of(slave, struct sh_qspi_slave, slave);
79 static void sh_qspi_init(struct sh_qspi_slave *ss)
82 /* Set master mode only */
83 writeb(SPCR_MSTR, &ss->regs->spcr);
85 /* Set SSL signal level */
86 writeb(0x00, &ss->regs->sslp);
88 /* Set MOSI signal value when transfer is in idle state */
89 writeb(SPPCR_IO3FV|SPPCR_IO2FV, &ss->regs->sppcr);
91 /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
92 writeb(0x01, &ss->regs->spbr);
94 /* Disable Dummy Data Transmission */
95 writeb(0x00, &ss->regs->spdcr);
97 /* Set clock delay value */
98 writeb(0x00, &ss->regs->spckd);
100 /* Set SSL negation delay value */
101 writeb(0x00, &ss->regs->sslnd);
103 /* Set next-access delay value */
104 writeb(0x00, &ss->regs->spnd);
106 /* Set equence command */
107 writew(SPCMD_INIT2, &ss->regs->spcmd0);
109 /* Reset transfer and receive Buffer */
110 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
112 /* Clear transfer and receive Buffer control bit */
113 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
115 /* Set equence control method. Use equence0 only */
116 writeb(0x00, &ss->regs->spscr);
118 /* Enable SPI function */
119 setbits_8(&ss->regs->spcr, SPCR_SPE);
122 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
127 void spi_cs_activate(struct spi_slave *slave)
129 struct sh_qspi_slave *ss = to_sh_qspi(slave);
131 /* Set master mode only */
132 writeb(SPCR_MSTR, &ss->regs->spcr);
135 writew(SPCMD_INIT1, &ss->regs->spcmd0);
137 /* Reset transfer and receive Buffer */
138 setbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
140 /* Clear transfer and receive Buffer control bit */
141 clrbits_8(&ss->regs->spbfcr, SPBFCR_TXRST|SPBFCR_RXRST);
143 /* Set equence control method. Use equence0 only */
144 writeb(0x00, &ss->regs->spscr);
146 /* Enable SPI function */
147 setbits_8(&ss->regs->spcr, SPCR_SPE);
150 void spi_cs_deactivate(struct spi_slave *slave)
152 struct sh_qspi_slave *ss = to_sh_qspi(slave);
154 /* Disable SPI Function */
155 clrbits_8(&ss->regs->spcr, SPCR_SPE);
163 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
164 unsigned int max_hz, unsigned int mode)
166 struct sh_qspi_slave *ss;
168 if (!spi_cs_is_valid(bus, cs))
171 ss = spi_alloc_slave(struct sh_qspi_slave, bus, cs);
173 printf("SPI_error: Fail to allocate sh_qspi_slave\n");
177 ss->regs = (struct sh_qspi_regs *)SH_QSPI_BASE;
185 void spi_free_slave(struct spi_slave *slave)
187 struct sh_qspi_slave *spi = to_sh_qspi(slave);
192 int spi_claim_bus(struct spi_slave *slave)
197 void spi_release_bus(struct spi_slave *slave)
201 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
202 void *din, unsigned long flags)
204 struct sh_qspi_slave *ss = to_sh_qspi(slave);
207 u8 dtdata = 0, drdata;
208 u8 *tdata = &dtdata, *rdata = &drdata;
209 u32 *spbmul0 = &ss->regs->spbmul0;
211 if (dout == NULL && din == NULL) {
212 if (flags & SPI_XFER_END)
213 spi_cs_deactivate(slave);
218 printf("%s: bitlen is not 8bit alined %d", __func__, bitlen);
224 if (flags & SPI_XFER_BEGIN) {
225 spi_cs_activate(slave);
227 /* Set 1048576 byte */
228 writel(0x100000, spbmul0);
231 if (flags & SPI_XFER_END)
232 writel(nbyte, spbmul0);
242 * Check if there is 32 Byte chunk and if there is, transfer
243 * it in one burst, otherwise transfer on byte-by-byte basis.
245 chunk = (nbyte >= 32) ? 32 : 1;
247 clrsetbits_8(&ss->regs->spbfcr, SPBFCR_TXTRG | SPBFCR_RXTRG,
248 chunk == 32 ? SPBFCR_TXTRG | SPBFCR_RXTRG : 0);
250 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPTEF,
255 for (i = 0; i < chunk; i++) {
256 writeb(*tdata, &ss->regs->spdr);
261 ret = wait_for_bit_8(&ss->regs->spsr, SPSR_SPRFF,
266 for (i = 0; i < chunk; i++) {
267 *rdata = readb(&ss->regs->spdr);
275 if (flags & SPI_XFER_END)
276 spi_cs_deactivate(slave);