git.sur5r.net Git - u-boot/blob - drivers/spi/sh_spi.c

   1 /*
   2  * SH SPI driver
   3  *
   4  * Copyright (C) 2011-2012 Renesas Solutions Corp.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 #include <common.h>
  10 #include <console.h>
  11 #include <malloc.h>
  12 #include <spi.h>
  13 #include <asm/io.h>
  14 #include "sh_spi.h"
  15
  16 static void sh_spi_write(unsigned long data, unsigned long *reg)
  17 {
  18         writel(data, reg);
  19 }
  20
  21 static unsigned long sh_spi_read(unsigned long *reg)
  22 {
  23         return readl(reg);
  24 }
  25
  26 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
  27 {
  28         unsigned long tmp;
  29
  30         tmp = sh_spi_read(reg);
  31         tmp |= val;
  32         sh_spi_write(tmp, reg);
  33 }
  34
  35 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
  36 {
  37         unsigned long tmp;
  38
  39         tmp = sh_spi_read(reg);
  40         tmp &= ~val;
  41         sh_spi_write(tmp, reg);
  42 }
  43
  44 static void clear_fifo(struct sh_spi *ss)
  45 {
  46         sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
  47         sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
  48 }
  49
  50 static int recvbuf_wait(struct sh_spi *ss)
  51 {
  52         while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
  53                 if (ctrlc())
  54                         return 1;
  55                 udelay(10);
  56         }
  57         return 0;
  58 }
  59
  60 static int write_fifo_empty_wait(struct sh_spi *ss)
  61 {
  62         while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
  63                 if (ctrlc())
  64                         return 1;
  65                 udelay(10);
  66         }
  67         return 0;
  68 }
  69
  70 void spi_init(void)
  71 {
  72 }
  73
  74 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
  75 {
  76         unsigned long val = 0;
  77
  78         if (cs & 0x01)
  79                 val |= SH_SPI_SSS0;
  80         if (cs & 0x02)
  81                 val |= SH_SPI_SSS1;
  82
  83         sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
  84         sh_spi_set_bit(val, &ss->regs->cr4);
  85 }
  86
  87 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  88                 unsigned int max_hz, unsigned int mode)
  89 {
  90         struct sh_spi *ss;
  91
  92         if (!spi_cs_is_valid(bus, cs))
  93                 return NULL;
  94
  95         ss = spi_alloc_slave(struct sh_spi, bus, cs);
  96         if (!ss)
  97                 return NULL;
  98
  99         ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
 100
 101         /* SPI sycle stop */
 102         sh_spi_write(0xfe, &ss->regs->cr1);
 103         /* CR1 init */
 104         sh_spi_write(0x00, &ss->regs->cr1);
 105         /* CR3 init */
 106         sh_spi_write(0x00, &ss->regs->cr3);
 107         sh_spi_set_cs(ss, cs);
 108
 109         clear_fifo(ss);
 110
 111         /* 1/8 clock */
 112         sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
 113         udelay(10);
 114
 115         return &ss->slave;
 116 }
 117
 118 void spi_free_slave(struct spi_slave *slave)
 119 {
 120         struct sh_spi *spi = to_sh_spi(slave);
 121
 122         free(spi);
 123 }
 124
 125 int spi_claim_bus(struct spi_slave *slave)
 126 {
 127         return 0;
 128 }
 129
 130 void spi_release_bus(struct spi_slave *slave)
 131 {
 132         struct sh_spi *ss = to_sh_spi(slave);
 133
 134         sh_spi_write(sh_spi_read(&ss->regs->cr1) &
 135                 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
 136 }
 137
 138 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
 139                         unsigned int len, unsigned long flags)
 140 {
 141         int i, cur_len, ret = 0;
 142         int remain = (int)len;
 143
 144         if (len >= SH_SPI_FIFO_SIZE)
 145                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 146
 147         while (remain > 0) {
 148                 cur_len = (remain < SH_SPI_FIFO_SIZE) ?
 149                                 remain : SH_SPI_FIFO_SIZE;
 150                 for (i = 0; i < cur_len &&
 151                         !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
 152                         !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
 153                                 i++)
 154                         sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
 155
 156                 cur_len = i;
 157
 158                 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
 159                         /* Abort the transaction */
 160                         flags |= SPI_XFER_END;
 161                         sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
 162                         ret = 1;
 163                         break;
 164                 }
 165
 166                 remain -= cur_len;
 167                 tx_data += cur_len;
 168
 169                 if (remain > 0)
 170                         write_fifo_empty_wait(ss);
 171         }
 172
 173         if (flags & SPI_XFER_END) {
 174                 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
 175                 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 176                 udelay(100);
 177                 write_fifo_empty_wait(ss);
 178         }
 179
 180         return ret;
 181 }
 182
 183 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
 184                           unsigned int len, unsigned long flags)
 185 {
 186         int i;
 187
 188         if (len > SH_SPI_MAX_BYTE)
 189                 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
 190         else
 191                 sh_spi_write(len, &ss->regs->cr3);
 192
 193         sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
 194         sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
 195
 196         for (i = 0; i < len; i++) {
 197                 if (recvbuf_wait(ss))
 198                         return 0;
 199
 200                 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
 201         }
 202         sh_spi_write(0, &ss->regs->cr3);
 203
 204         return 0;
 205 }
 206
 207 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 208                 void *din, unsigned long flags)
 209 {
 210         struct sh_spi *ss = to_sh_spi(slave);
 211         const unsigned char *tx_data = dout;
 212         unsigned char *rx_data = din;
 213         unsigned int len = bitlen / 8;
 214         int ret = 0;
 215
 216         if (flags & SPI_XFER_BEGIN)
 217                 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
 218                                 &ss->regs->cr1);
 219
 220         if (tx_data)
 221                 ret = sh_spi_send(ss, tx_data, len, flags);
 222
 223         if (ret == 0 && rx_data)
 224                 ret = sh_spi_receive(ss, rx_data, len, flags);
 225
 226         if (flags & SPI_XFER_END) {
 227                 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
 228                 udelay(100);
 229
 230                 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
 231                                  &ss->regs->cr1);
 232                 clear_fifo(ss);
 233         }
 234
 235         return ret;
 236 }
 237
 238 int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
 239 {
 240         if (!bus && cs < SH_SPI_NUM_CS)
 241                 return 1;
 242         else
 243                 return 0;
 244 }
 245
 246 void spi_cs_activate(struct spi_slave *slave)
 247 {
 248
 249 }
 250
 251 void spi_cs_deactivate(struct spi_slave *slave)
 252 {
 253
 254 }