git.sur5r.net Git - u-boot/blob - drivers/spi/stm32_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016
   4  *
   5  * Michael Kurz, <michi.kurz@gmail.com>
   6  *
   7  * STM32 QSPI driver
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <spi.h>
  13 #include <spi_flash.h>
  14 #include <asm/io.h>
  15 #include <dm.h>
  16 #include <errno.h>
  17 #include <asm/arch/stm32.h>
  18 #include <clk.h>
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 struct stm32_qspi_regs {
  23         u32 cr;         /* 0x00 */
  24         u32 dcr;        /* 0x04 */
  25         u32 sr;         /* 0x08 */
  26         u32 fcr;        /* 0x0C */
  27         u32 dlr;        /* 0x10 */
  28         u32 ccr;        /* 0x14 */
  29         u32 ar;         /* 0x18 */
  30         u32 abr;        /* 0x1C */
  31         u32 dr;         /* 0x20 */
  32         u32 psmkr;      /* 0x24 */
  33         u32 psmar;      /* 0x28 */
  34         u32 pir;        /* 0x2C */
  35         u32 lptr;       /* 0x30 */
  36 };
  37
  38 /*
  39  * QUADSPI control register
  40  */
  41 #define STM32_QSPI_CR_EN                BIT(0)
  42 #define STM32_QSPI_CR_ABORT             BIT(1)
  43 #define STM32_QSPI_CR_DMAEN             BIT(2)
  44 #define STM32_QSPI_CR_TCEN              BIT(3)
  45 #define STM32_QSPI_CR_SSHIFT            BIT(4)
  46 #define STM32_QSPI_CR_DFM               BIT(6)
  47 #define STM32_QSPI_CR_FSEL              BIT(7)
  48 #define STM32_QSPI_CR_FTHRES_MASK       GENMASK(4, 0)
  49 #define STM32_QSPI_CR_FTHRES_SHIFT      (8)
  50 #define STM32_QSPI_CR_TEIE              BIT(16)
  51 #define STM32_QSPI_CR_TCIE              BIT(17)
  52 #define STM32_QSPI_CR_FTIE              BIT(18)
  53 #define STM32_QSPI_CR_SMIE              BIT(19)
  54 #define STM32_QSPI_CR_TOIE              BIT(20)
  55 #define STM32_QSPI_CR_APMS              BIT(22)
  56 #define STM32_QSPI_CR_PMM               BIT(23)
  57 #define STM32_QSPI_CR_PRESCALER_MASK    GENMASK(7, 0)
  58 #define STM32_QSPI_CR_PRESCALER_SHIFT   (24)
  59
  60 /*
  61  * QUADSPI device configuration register
  62  */
  63 #define STM32_QSPI_DCR_CKMODE           BIT(0)
  64 #define STM32_QSPI_DCR_CSHT_MASK        GENMASK(2, 0)
  65 #define STM32_QSPI_DCR_CSHT_SHIFT       (8)
  66 #define STM32_QSPI_DCR_FSIZE_MASK       GENMASK(4, 0)
  67 #define STM32_QSPI_DCR_FSIZE_SHIFT      (16)
  68
  69 /*
  70  * QUADSPI status register
  71  */
  72 #define STM32_QSPI_SR_TEF               BIT(0)
  73 #define STM32_QSPI_SR_TCF               BIT(1)
  74 #define STM32_QSPI_SR_FTF               BIT(2)
  75 #define STM32_QSPI_SR_SMF               BIT(3)
  76 #define STM32_QSPI_SR_TOF               BIT(4)
  77 #define STM32_QSPI_SR_BUSY              BIT(5)
  78 #define STM32_QSPI_SR_FLEVEL_MASK       GENMASK(5, 0)
  79 #define STM32_QSPI_SR_FLEVEL_SHIFT      (8)
  80
  81 /*
  82  * QUADSPI flag clear register
  83  */
  84 #define STM32_QSPI_FCR_CTEF             BIT(0)
  85 #define STM32_QSPI_FCR_CTCF             BIT(1)
  86 #define STM32_QSPI_FCR_CSMF             BIT(3)
  87 #define STM32_QSPI_FCR_CTOF             BIT(4)
  88
  89 /*
  90  * QUADSPI communication configuration register
  91  */
  92 #define STM32_QSPI_CCR_DDRM             BIT(31)
  93 #define STM32_QSPI_CCR_DHHC             BIT(30)
  94 #define STM32_QSPI_CCR_SIOO             BIT(28)
  95 #define STM32_QSPI_CCR_FMODE_SHIFT      (26)
  96 #define STM32_QSPI_CCR_DMODE_SHIFT      (24)
  97 #define STM32_QSPI_CCR_DCYC_SHIFT       (18)
  98 #define STM32_QSPI_CCR_DCYC_MASK        GENMASK(4, 0)
  99 #define STM32_QSPI_CCR_ABSIZE_SHIFT     (16)
 100 #define STM32_QSPI_CCR_ABMODE_SHIFT     (14)
 101 #define STM32_QSPI_CCR_ADSIZE_SHIFT     (12)
 102 #define STM32_QSPI_CCR_ADMODE_SHIFT     (10)
 103 #define STM32_QSPI_CCR_IMODE_SHIFT      (8)
 104 #define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
 105
 106 enum STM32_QSPI_CCR_IMODE {
 107         STM32_QSPI_CCR_IMODE_NONE = 0,
 108         STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
 109         STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
 110         STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
 111 };
 112
 113 enum STM32_QSPI_CCR_ADMODE {
 114         STM32_QSPI_CCR_ADMODE_NONE = 0,
 115         STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
 116         STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
 117         STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
 118 };
 119
 120 enum STM32_QSPI_CCR_ADSIZE {
 121         STM32_QSPI_CCR_ADSIZE_8BIT = 0,
 122         STM32_QSPI_CCR_ADSIZE_16BIT = 1,
 123         STM32_QSPI_CCR_ADSIZE_24BIT = 2,
 124         STM32_QSPI_CCR_ADSIZE_32BIT = 3,
 125 };
 126
 127 enum STM32_QSPI_CCR_ABMODE {
 128         STM32_QSPI_CCR_ABMODE_NONE = 0,
 129         STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
 130         STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
 131         STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
 132 };
 133
 134 enum STM32_QSPI_CCR_ABSIZE {
 135         STM32_QSPI_CCR_ABSIZE_8BIT = 0,
 136         STM32_QSPI_CCR_ABSIZE_16BIT = 1,
 137         STM32_QSPI_CCR_ABSIZE_24BIT = 2,
 138         STM32_QSPI_CCR_ABSIZE_32BIT = 3,
 139 };
 140
 141 enum STM32_QSPI_CCR_DMODE {
 142         STM32_QSPI_CCR_DMODE_NONE = 0,
 143         STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
 144         STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
 145         STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
 146 };
 147
 148 enum STM32_QSPI_CCR_FMODE {
 149         STM32_QSPI_CCR_IND_WRITE = 0,
 150         STM32_QSPI_CCR_IND_READ = 1,
 151         STM32_QSPI_CCR_AUTO_POLL = 2,
 152         STM32_QSPI_CCR_MEM_MAP = 3,
 153 };
 154
 155 /* default SCK frequency, unit: HZ */
 156 #define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
 157
 158 struct stm32_qspi_platdata {
 159         u32 base;
 160         u32 memory_map;
 161         u32 max_hz;
 162 };
 163
 164 struct stm32_qspi_priv {
 165         struct stm32_qspi_regs *regs;
 166         ulong clock_rate;
 167         u32 max_hz;
 168         u32 mode;
 169
 170         u32 command;
 171         u32 address;
 172         u32 dummycycles;
 173 #define CMD_HAS_ADR     BIT(24)
 174 #define CMD_HAS_DUMMY   BIT(25)
 175 #define CMD_HAS_DATA    BIT(26)
 176 };
 177
 178 static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
 179 {
 180         clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 181 }
 182
 183 static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
 184 {
 185         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
 186 }
 187
 188 static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
 189 {
 190         while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
 191                 ;
 192 }
 193
 194 static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
 195 {
 196         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
 197                 ;
 198 }
 199
 200 static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
 201 {
 202         while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
 203                 ;
 204 }
 205
 206 static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
 207 {
 208         u32 fsize = fls(size) - 1;
 209
 210         clrsetbits_le32(&priv->regs->dcr,
 211                         STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
 212                         fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
 213 }
 214
 215 static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
 216 {
 217         unsigned int ccr_reg = 0;
 218         u8 imode, admode, dmode;
 219         u32 mode = priv->mode;
 220         u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
 221
 222         imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
 223         admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
 224
 225         if (mode & SPI_RX_QUAD) {
 226                 dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
 227                 if (mode & SPI_TX_QUAD) {
 228                         imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
 229                         admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
 230                 }
 231         } else if (mode & SPI_RX_DUAL) {
 232                 dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
 233                 if (mode & SPI_TX_DUAL) {
 234                         imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
 235                         admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
 236                 }
 237         } else {
 238                 dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
 239         }
 240
 241         if (priv->command & CMD_HAS_DATA)
 242                 ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
 243
 244         if (priv->command & CMD_HAS_DUMMY)
 245                 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
 246                                 << STM32_QSPI_CCR_DCYC_SHIFT);
 247
 248         if (priv->command & CMD_HAS_ADR) {
 249                 ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
 250                                 << STM32_QSPI_CCR_ADSIZE_SHIFT);
 251                 ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
 252         }
 253         ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
 254         ccr_reg |= cmd;
 255         return ccr_reg;
 256 }
 257
 258 static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
 259                                     struct spi_flash *flash)
 260 {
 261         unsigned int ccr_reg;
 262
 263         priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
 264                         | CMD_HAS_DUMMY;
 265         priv->dummycycles = flash->dummy_byte * 8;
 266
 267         ccr_reg = _stm32_qspi_gen_ccr(priv);
 268         ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
 269
 270         _stm32_qspi_wait_for_not_busy(priv);
 271
 272         writel(ccr_reg, &priv->regs->ccr);
 273
 274         priv->dummycycles = 0;
 275 }
 276
 277 static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
 278 {
 279         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
 280 }
 281
 282 static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
 283                                         u32 length)
 284 {
 285         writel(length - 1, &priv->regs->dlr);
 286 }
 287
 288 static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
 289 {
 290         writel(cr_reg, &priv->regs->ccr);
 291
 292         if (priv->command & CMD_HAS_ADR)
 293                 writel(priv->address, &priv->regs->ar);
 294 }
 295
 296 static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
 297                             struct spi_flash *flash, unsigned int bitlen,
 298                             const u8 *dout, u8 *din, unsigned long flags)
 299 {
 300         unsigned int words = bitlen / 8;
 301         u32 ccr_reg;
 302         int i;
 303
 304         if (flags & SPI_XFER_MMAP) {
 305                 _stm32_qspi_enable_mmap(priv, flash);
 306                 return 0;
 307         } else if (flags & SPI_XFER_MMAP_END) {
 308                 _stm32_qspi_disable_mmap(priv);
 309                 return 0;
 310         }
 311
 312         if (bitlen == 0)
 313                 return -1;
 314
 315         if (bitlen % 8) {
 316                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 317                 return -1;
 318         }
 319
 320         if (dout && din) {
 321                 debug("spi_xfer: QSPI cannot have data in and data out set\n");
 322                 return -1;
 323         }
 324
 325         if (!dout && (flags & SPI_XFER_BEGIN)) {
 326                 debug("spi_xfer: QSPI transfer must begin with command\n");
 327                 return -1;
 328         }
 329
 330         if (dout) {
 331                 if (flags & SPI_XFER_BEGIN) {
 332                         /* data is command */
 333                         priv->command = dout[0] | CMD_HAS_DATA;
 334                         if (words >= 4) {
 335                                 /* address is here too */
 336                                 priv->address = (dout[1] << 16) |
 337                                                 (dout[2] << 8) | dout[3];
 338                                 priv->command |= CMD_HAS_ADR;
 339                         }
 340
 341                         if (words > 4) {
 342                                 /* rest is dummy bytes */
 343                                 priv->dummycycles = (words - 4) * 8;
 344                                 priv->command |= CMD_HAS_DUMMY;
 345                         }
 346
 347                         if (flags & SPI_XFER_END) {
 348                                 /* command without data */
 349                                 priv->command &= ~(CMD_HAS_DATA);
 350                         }
 351                 }
 352
 353                 if (flags & SPI_XFER_END) {
 354                         ccr_reg = _stm32_qspi_gen_ccr(priv);
 355                         ccr_reg |= STM32_QSPI_CCR_IND_WRITE
 356                                         << STM32_QSPI_CCR_FMODE_SHIFT;
 357
 358                         _stm32_qspi_wait_for_not_busy(priv);
 359
 360                         if (priv->command & CMD_HAS_DATA)
 361                                 _stm32_qspi_set_xfer_length(priv, words);
 362
 363                         _stm32_qspi_start_xfer(priv, ccr_reg);
 364
 365                         debug("%s: write: ccr:0x%08x adr:0x%08x\n",
 366                               __func__, priv->regs->ccr, priv->regs->ar);
 367
 368                         if (priv->command & CMD_HAS_DATA) {
 369                                 _stm32_qspi_wait_for_ftf(priv);
 370
 371                                 debug("%s: words:%d data:", __func__, words);
 372
 373                                 i = 0;
 374                                 while (words > i) {
 375                                         writeb(dout[i], &priv->regs->dr);
 376                                         debug("%02x ", dout[i]);
 377                                         i++;
 378                                 }
 379                                 debug("\n");
 380
 381                                 _stm32_qspi_wait_for_complete(priv);
 382                         } else {
 383                                 _stm32_qspi_wait_for_not_busy(priv);
 384                         }
 385                 }
 386         } else if (din) {
 387                 ccr_reg = _stm32_qspi_gen_ccr(priv);
 388                 ccr_reg |= STM32_QSPI_CCR_IND_READ
 389                                 << STM32_QSPI_CCR_FMODE_SHIFT;
 390
 391                 _stm32_qspi_wait_for_not_busy(priv);
 392
 393                 _stm32_qspi_set_xfer_length(priv, words);
 394
 395                 _stm32_qspi_start_xfer(priv, ccr_reg);
 396
 397                 debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
 398                       priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
 399
 400                 debug("%s: data:", __func__);
 401
 402                 i = 0;
 403                 while (words > i) {
 404                         din[i] = readb(&priv->regs->dr);
 405                         debug("%02x ", din[i]);
 406                         i++;
 407                 }
 408                 debug("\n");
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
 415 {
 416         struct fdt_resource res_regs, res_mem;
 417         struct stm32_qspi_platdata *plat = bus->platdata;
 418         const void *blob = gd->fdt_blob;
 419         int node = dev_of_offset(bus);
 420         int ret;
 421
 422         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 423                                      "QuadSPI", &res_regs);
 424         if (ret) {
 425                 debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
 426                 return -ENOMEM;
 427         }
 428         ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 429                                      "QuadSPI-memory", &res_mem);
 430         if (ret) {
 431                 debug("Error: can't get mmap base address(ret = %d)!\n", ret);
 432                 return -ENOMEM;
 433         }
 434
 435         plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
 436                                         STM32_QSPI_DEFAULT_SCK_FREQ);
 437
 438         plat->base = res_regs.start;
 439         plat->memory_map = res_mem.start;
 440
 441         debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
 442               __func__,
 443               plat->base,
 444               plat->memory_map,
 445               plat->max_hz
 446               );
 447
 448         return 0;
 449 }
 450
 451 static int stm32_qspi_probe(struct udevice *bus)
 452 {
 453         struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
 454         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 455         struct dm_spi_bus *dm_spi_bus;
 456         struct clk clk;
 457         int ret;
 458
 459         dm_spi_bus = bus->uclass_priv;
 460
 461         dm_spi_bus->max_hz = plat->max_hz;
 462
 463         priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
 464
 465         priv->max_hz = plat->max_hz;
 466
 467         ret = clk_get_by_index(bus, 0, &clk);
 468         if (ret < 0)
 469                 return ret;
 470
 471         ret = clk_enable(&clk);
 472
 473         if (ret) {
 474                 dev_err(bus, "failed to enable clock\n");
 475                 return ret;
 476         }
 477
 478         priv->clock_rate = clk_get_rate(&clk);
 479         if (priv->clock_rate < 0) {
 480                 clk_disable(&clk);
 481                 return priv->clock_rate;
 482         }
 483
 484
 485         setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
 486
 487         return 0;
 488 }
 489
 490 static int stm32_qspi_remove(struct udevice *bus)
 491 {
 492         return 0;
 493 }
 494
 495 static int stm32_qspi_claim_bus(struct udevice *dev)
 496 {
 497         struct stm32_qspi_priv *priv;
 498         struct udevice *bus;
 499         struct spi_flash *flash;
 500
 501         bus = dev->parent;
 502         priv = dev_get_priv(bus);
 503         flash = dev_get_uclass_priv(dev);
 504
 505         _stm32_qspi_set_flash_size(priv, flash->size);
 506
 507         _stm32_qspi_enable(priv);
 508
 509         return 0;
 510 }
 511
 512 static int stm32_qspi_release_bus(struct udevice *dev)
 513 {
 514         struct stm32_qspi_priv *priv;
 515         struct udevice *bus;
 516
 517         bus = dev->parent;
 518         priv = dev_get_priv(bus);
 519
 520         _stm32_qspi_disable(priv);
 521
 522         return 0;
 523 }
 524
 525 static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 526                            const void *dout, void *din, unsigned long flags)
 527 {
 528         struct stm32_qspi_priv *priv;
 529         struct udevice *bus;
 530         struct spi_flash *flash;
 531
 532         bus = dev->parent;
 533         priv = dev_get_priv(bus);
 534         flash = dev_get_uclass_priv(dev);
 535
 536         return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
 537                                 (u8 *)din, flags);
 538 }
 539
 540 static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
 541 {
 542         struct stm32_qspi_platdata *plat = bus->platdata;
 543         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 544         u32 qspi_clk = priv->clock_rate;
 545         u32 prescaler = 255;
 546         u32 csht;
 547
 548         if (speed > plat->max_hz)
 549                 speed = plat->max_hz;
 550
 551         if (speed > 0) {
 552                 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
 553                 if (prescaler > 255)
 554                         prescaler = 255;
 555                 else if (prescaler < 0)
 556                         prescaler = 0;
 557         }
 558
 559         csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
 560         csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
 561
 562         _stm32_qspi_wait_for_not_busy(priv);
 563
 564         clrsetbits_le32(&priv->regs->cr,
 565                         STM32_QSPI_CR_PRESCALER_MASK <<
 566                         STM32_QSPI_CR_PRESCALER_SHIFT,
 567                         prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
 568
 569         clrsetbits_le32(&priv->regs->dcr,
 570                         STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
 571                         csht << STM32_QSPI_DCR_CSHT_SHIFT);
 572
 573         debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
 574               (qspi_clk / (prescaler + 1)));
 575
 576         return 0;
 577 }
 578
 579 static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
 580 {
 581         struct stm32_qspi_priv *priv = dev_get_priv(bus);
 582
 583         _stm32_qspi_wait_for_not_busy(priv);
 584
 585         if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
 586                 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 587         else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
 588                 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
 589         else
 590                 return -ENODEV;
 591
 592         if (mode & SPI_CS_HIGH)
 593                 return -ENODEV;
 594
 595         if (mode & SPI_RX_QUAD)
 596                 priv->mode |= SPI_RX_QUAD;
 597         else if (mode & SPI_RX_DUAL)
 598                 priv->mode |= SPI_RX_DUAL;
 599         else
 600                 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
 601
 602         if (mode & SPI_TX_QUAD)
 603                 priv->mode |= SPI_TX_QUAD;
 604         else if (mode & SPI_TX_DUAL)
 605                 priv->mode |= SPI_TX_DUAL;
 606         else
 607                 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
 608
 609         debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
 610
 611         if (mode & SPI_RX_QUAD)
 612                 debug("quad, tx: ");
 613         else if (mode & SPI_RX_DUAL)
 614                 debug("dual, tx: ");
 615         else
 616                 debug("single, tx: ");
 617
 618         if (mode & SPI_TX_QUAD)
 619                 debug("quad\n");
 620         else if (mode & SPI_TX_DUAL)
 621                 debug("dual\n");
 622         else
 623                 debug("single\n");
 624
 625         return 0;
 626 }
 627
 628 static const struct dm_spi_ops stm32_qspi_ops = {
 629         .claim_bus      = stm32_qspi_claim_bus,
 630         .release_bus    = stm32_qspi_release_bus,
 631         .xfer           = stm32_qspi_xfer,
 632         .set_speed      = stm32_qspi_set_speed,
 633         .set_mode       = stm32_qspi_set_mode,
 634 };
 635
 636 static const struct udevice_id stm32_qspi_ids[] = {
 637         { .compatible = "st,stm32-qspi" },
 638         { }
 639 };
 640
 641 U_BOOT_DRIVER(stm32_qspi) = {
 642         .name   = "stm32_qspi",
 643         .id     = UCLASS_SPI,
 644         .of_match = stm32_qspi_ids,
 645         .ops    = &stm32_qspi_ops,
 646         .ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
 647         .platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
 648         .priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
 649         .probe  = stm32_qspi_probe,
 650         .remove = stm32_qspi_remove,
 651 };