2 * Copyright (c) 2010-2013 NVIDIA Corporation
3 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra20/tegra20_sflash.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define SPI_CMD_GO (1 << 30)
23 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
24 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
25 #define SPI_CMD_CK_SDA (1 << 21)
26 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
27 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
28 #define SPI_CMD_CS_POL (1 << 16)
29 #define SPI_CMD_TXEN (1 << 15)
30 #define SPI_CMD_RXEN (1 << 14)
31 #define SPI_CMD_CS_VAL (1 << 13)
32 #define SPI_CMD_CS_SOFT (1 << 12)
33 #define SPI_CMD_CS_DELAY (1 << 9)
34 #define SPI_CMD_CS3_EN (1 << 8)
35 #define SPI_CMD_CS2_EN (1 << 7)
36 #define SPI_CMD_CS1_EN (1 << 6)
37 #define SPI_CMD_CS0_EN (1 << 5)
38 #define SPI_CMD_BIT_LENGTH (1 << 4)
39 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
41 #define SPI_STAT_BSY (1 << 31)
42 #define SPI_STAT_RDY (1 << 30)
43 #define SPI_STAT_RXF_FLUSH (1 << 29)
44 #define SPI_STAT_TXF_FLUSH (1 << 28)
45 #define SPI_STAT_RXF_UNR (1 << 27)
46 #define SPI_STAT_TXF_OVF (1 << 26)
47 #define SPI_STAT_RXF_EMPTY (1 << 25)
48 #define SPI_STAT_RXF_FULL (1 << 24)
49 #define SPI_STAT_TXF_EMPTY (1 << 23)
50 #define SPI_STAT_TXF_FULL (1 << 22)
51 #define SPI_STAT_SEL_TXRX_N (1 << 16)
52 #define SPI_STAT_CUR_BLKCNT (1 << 15)
54 #define SPI_TIMEOUT 1000
55 #define TEGRA_SPI_MAX_FREQ 52000000
58 u32 command; /* SPI_COMMAND_0 register */
59 u32 status; /* SPI_STATUS_0 register */
60 u32 rx_cmp; /* SPI_RX_CMP_0 register */
61 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
62 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
63 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
64 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
67 struct tegra_spi_ctrl {
68 struct spi_regs *regs;
75 struct tegra_spi_slave {
76 struct spi_slave slave;
77 struct tegra_spi_ctrl *ctrl;
80 /* tegra20 only supports one SFLASH controller */
81 static struct tegra_spi_ctrl spi_ctrls[1];
83 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
85 return container_of(slave, struct tegra_spi_slave, slave);
88 int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
90 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
91 if (bus != 0 || cs != 0)
97 struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
98 unsigned int max_hz, unsigned int mode)
100 struct tegra_spi_slave *spi;
102 if (!spi_cs_is_valid(bus, cs)) {
103 printf("SPI error: unsupported bus %d / chip select %d\n",
108 if (max_hz > TEGRA_SPI_MAX_FREQ) {
109 printf("SPI error: unsupported frequency %d Hz. Max frequency"
110 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
114 spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
116 printf("SPI error: malloc of SPI structure failed\n");
119 spi->ctrl = &spi_ctrls[bus];
121 printf("SPI error: could not find controller for bus %d\n",
126 if (max_hz < spi->ctrl->freq) {
127 debug("%s: limiting frequency from %u to %u\n", __func__,
128 spi->ctrl->freq, max_hz);
129 spi->ctrl->freq = max_hz;
131 spi->ctrl->mode = mode;
136 void tegra20_spi_free_slave(struct spi_slave *slave)
138 struct tegra_spi_slave *spi = to_tegra_spi(slave);
143 int tegra20_spi_init(int *node_list, int count)
145 struct tegra_spi_ctrl *ctrl;
150 for (i = 0; i < count; i++) {
151 ctrl = &spi_ctrls[i];
154 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
156 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
157 debug("%s: no slink register found\n", __func__);
160 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
161 "spi-max-frequency", 0);
163 debug("%s: no slink max frequency found\n", __func__);
167 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
168 if (ctrl->periph_id == PERIPH_ID_NONE) {
169 debug("%s: could not decode periph id\n", __func__);
175 debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
176 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
181 int tegra20_spi_claim_bus(struct spi_slave *slave)
183 struct tegra_spi_slave *spi = to_tegra_spi(slave);
184 struct spi_regs *regs = spi->ctrl->regs;
187 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
188 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
191 /* Clear stale status here */
192 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
193 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
194 writel(reg, ®s->status);
195 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
198 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
200 reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
201 if (spi->ctrl->mode & 2)
202 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
203 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
204 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
205 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
208 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
211 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
212 pinmux_tristate_disable(PINGRP_LSPI);
213 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
218 void tegra20_spi_cs_activate(struct spi_slave *slave)
220 struct tegra_spi_slave *spi = to_tegra_spi(slave);
221 struct spi_regs *regs = spi->ctrl->regs;
223 /* CS is negated on Tegra, so drive a 1 to get a 0 */
224 setbits_le32(®s->command, SPI_CMD_CS_VAL);
227 void tegra20_spi_cs_deactivate(struct spi_slave *slave)
229 struct tegra_spi_slave *spi = to_tegra_spi(slave);
230 struct spi_regs *regs = spi->ctrl->regs;
232 /* CS is negated on Tegra, so drive a 0 to get a 1 */
233 clrbits_le32(®s->command, SPI_CMD_CS_VAL);
236 int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
237 const void *data_out, void *data_in, unsigned long flags)
239 struct tegra_spi_slave *spi = to_tegra_spi(slave);
240 struct spi_regs *regs = spi->ctrl->regs;
241 u32 reg, tmpdout, tmpdin = 0;
242 const u8 *dout = data_out;
247 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
248 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
251 num_bytes = bitlen / 8;
255 reg = readl(®s->status);
256 writel(reg, ®s->status); /* Clear all SPI events via R/W */
257 debug("spi_xfer entry: STATUS = %08x\n", reg);
259 reg = readl(®s->command);
260 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
261 writel(reg, ®s->command);
262 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
264 if (flags & SPI_XFER_BEGIN)
265 spi_cs_activate(slave);
267 /* handle data in 32-bit chunks */
268 while (num_bytes > 0) {
274 bytes = (num_bytes > 4) ? 4 : num_bytes;
277 for (i = 0; i < bytes; ++i)
278 tmpdout = (tmpdout << 8) | dout[i];
285 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
287 writel(tmpdout, ®s->tx_fifo);
288 setbits_le32(®s->command, SPI_CMD_GO);
291 * Wait for SPI transmit FIFO to empty, or to time out.
292 * The RX FIFO status will be read and cleared last
294 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
297 status = readl(®s->status);
299 /* We can exit when we've had both RX and TX activity */
300 if (is_read && (status & SPI_STAT_TXF_EMPTY))
303 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
307 else if (!(status & SPI_STAT_RXF_EMPTY)) {
308 tmpdin = readl(®s->rx_fifo);
311 /* swap bytes read in */
313 for (i = bytes - 1; i >= 0; --i) {
314 din[i] = tmpdin & 0xff;
322 if (tm >= SPI_TIMEOUT)
325 /* clear ACK RDY, etc. bits */
326 writel(readl(®s->status), ®s->status);
329 if (flags & SPI_XFER_END)
330 spi_cs_deactivate(slave);
332 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
333 tmpdin, readl(®s->status));
336 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);