2 * Copyright (c) 2010-2013 NVIDIA Corporation
3 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/pinmux.h>
16 #include <asm/arch-tegra/clk_rst.h>
19 #include "tegra_spi.h"
21 DECLARE_GLOBAL_DATA_PTR;
23 #define SPI_CMD_GO BIT(30)
24 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
25 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
26 #define SPI_CMD_CK_SDA BIT(21)
27 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
28 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
29 #define SPI_CMD_CS_POL BIT(16)
30 #define SPI_CMD_TXEN BIT(15)
31 #define SPI_CMD_RXEN BIT(14)
32 #define SPI_CMD_CS_VAL BIT(13)
33 #define SPI_CMD_CS_SOFT BIT(12)
34 #define SPI_CMD_CS_DELAY BIT(9)
35 #define SPI_CMD_CS3_EN BIT(8)
36 #define SPI_CMD_CS2_EN BIT(7)
37 #define SPI_CMD_CS1_EN BIT(6)
38 #define SPI_CMD_CS0_EN BIT(5)
39 #define SPI_CMD_BIT_LENGTH BIT(4)
40 #define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
42 #define SPI_STAT_BSY BIT(31)
43 #define SPI_STAT_RDY BIT(30)
44 #define SPI_STAT_RXF_FLUSH BIT(29)
45 #define SPI_STAT_TXF_FLUSH BIT(28)
46 #define SPI_STAT_RXF_UNR BIT(27)
47 #define SPI_STAT_TXF_OVF BIT(26)
48 #define SPI_STAT_RXF_EMPTY BIT(25)
49 #define SPI_STAT_RXF_FULL BIT(24)
50 #define SPI_STAT_TXF_EMPTY BIT(23)
51 #define SPI_STAT_TXF_FULL BIT(22)
52 #define SPI_STAT_SEL_TXRX_N BIT(16)
53 #define SPI_STAT_CUR_BLKCNT BIT(15)
55 #define SPI_TIMEOUT 1000
56 #define TEGRA_SPI_MAX_FREQ 52000000
59 u32 command; /* SPI_COMMAND_0 register */
60 u32 status; /* SPI_STATUS_0 register */
61 u32 rx_cmp; /* SPI_RX_CMP_0 register */
62 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
63 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
64 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
65 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
68 struct tegra20_sflash_priv {
69 struct spi_regs *regs;
74 int last_transaction_us;
77 int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
78 struct spi_cs_info *info)
80 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
87 static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
89 struct tegra_spi_platdata *plat = bus->platdata;
90 const void *blob = gd->fdt_blob;
91 int node = dev_of_offset(bus);
93 plat->base = devfdt_get_addr(bus);
94 plat->periph_id = clock_decode_periph_id(blob, node);
96 if (plat->periph_id == PERIPH_ID_NONE) {
97 debug("%s: could not decode periph id %d\n", __func__,
99 return -FDT_ERR_NOTFOUND;
102 /* Use 500KHz as a suitable default */
103 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
105 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
106 "spi-deactivate-delay", 0);
107 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
108 __func__, plat->base, plat->periph_id, plat->frequency,
109 plat->deactivate_delay_us);
114 static int tegra20_sflash_probe(struct udevice *bus)
116 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
117 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
119 priv->regs = (struct spi_regs *)plat->base;
121 priv->last_transaction_us = timer_get_us();
122 priv->freq = plat->frequency;
123 priv->periph_id = plat->periph_id;
125 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
126 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
132 static int tegra20_sflash_claim_bus(struct udevice *dev)
134 struct udevice *bus = dev->parent;
135 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
136 struct spi_regs *regs = priv->regs;
139 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
140 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
143 /* Clear stale status here */
144 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
145 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
146 writel(reg, ®s->status);
147 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
150 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
152 reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
154 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
155 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
156 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
157 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
160 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
163 pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
164 pinmux_tristate_disable(PMUX_PINGRP_LSPI);
165 pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
170 static void spi_cs_activate(struct udevice *dev)
172 struct udevice *bus = dev->parent;
173 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
174 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
176 /* If it's too soon to do another transaction, wait */
177 if (pdata->deactivate_delay_us &&
178 priv->last_transaction_us) {
179 ulong delay_us; /* The delay completed so far */
180 delay_us = timer_get_us() - priv->last_transaction_us;
181 if (delay_us < pdata->deactivate_delay_us)
182 udelay(pdata->deactivate_delay_us - delay_us);
185 /* CS is negated on Tegra, so drive a 1 to get a 0 */
186 setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
189 static void spi_cs_deactivate(struct udevice *dev)
191 struct udevice *bus = dev->parent;
192 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
193 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
195 /* CS is negated on Tegra, so drive a 0 to get a 1 */
196 clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
198 /* Remember time of this transaction so we can honour the bus delay */
199 if (pdata->deactivate_delay_us)
200 priv->last_transaction_us = timer_get_us();
203 static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
204 const void *data_out, void *data_in,
207 struct udevice *bus = dev->parent;
208 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
209 struct spi_regs *regs = priv->regs;
210 u32 reg, tmpdout, tmpdin = 0;
211 const u8 *dout = data_out;
216 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
217 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
220 num_bytes = bitlen / 8;
224 reg = readl(®s->status);
225 writel(reg, ®s->status); /* Clear all SPI events via R/W */
226 debug("spi_xfer entry: STATUS = %08x\n", reg);
228 reg = readl(®s->command);
229 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
230 writel(reg, ®s->command);
231 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
233 if (flags & SPI_XFER_BEGIN)
234 spi_cs_activate(dev);
236 /* handle data in 32-bit chunks */
237 while (num_bytes > 0) {
243 bytes = (num_bytes > 4) ? 4 : num_bytes;
246 for (i = 0; i < bytes; ++i)
247 tmpdout = (tmpdout << 8) | dout[i];
254 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
256 writel(tmpdout, ®s->tx_fifo);
257 setbits_le32(®s->command, SPI_CMD_GO);
260 * Wait for SPI transmit FIFO to empty, or to time out.
261 * The RX FIFO status will be read and cleared last
263 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
266 status = readl(®s->status);
268 /* We can exit when we've had both RX and TX activity */
269 if (is_read && (status & SPI_STAT_TXF_EMPTY))
272 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
276 else if (!(status & SPI_STAT_RXF_EMPTY)) {
277 tmpdin = readl(®s->rx_fifo);
280 /* swap bytes read in */
282 for (i = bytes - 1; i >= 0; --i) {
283 din[i] = tmpdin & 0xff;
291 if (tm >= SPI_TIMEOUT)
294 /* clear ACK RDY, etc. bits */
295 writel(readl(®s->status), ®s->status);
298 if (flags & SPI_XFER_END)
299 spi_cs_deactivate(dev);
301 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
302 tmpdin, readl(®s->status));
305 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
312 static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
314 struct tegra_spi_platdata *plat = bus->platdata;
315 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
317 if (speed > plat->frequency)
318 speed = plat->frequency;
320 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
325 static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
327 struct tegra20_sflash_priv *priv = dev_get_priv(bus);
330 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
335 static const struct dm_spi_ops tegra20_sflash_ops = {
336 .claim_bus = tegra20_sflash_claim_bus,
337 .xfer = tegra20_sflash_xfer,
338 .set_speed = tegra20_sflash_set_speed,
339 .set_mode = tegra20_sflash_set_mode,
340 .cs_info = tegra20_sflash_cs_info,
343 static const struct udevice_id tegra20_sflash_ids[] = {
344 { .compatible = "nvidia,tegra20-sflash" },
348 U_BOOT_DRIVER(tegra20_sflash) = {
349 .name = "tegra20_sflash",
351 .of_match = tegra20_sflash_ids,
352 .ops = &tegra20_sflash_ops,
353 .ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
354 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
355 .priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
356 .probe = tegra20_sflash_probe,