2 * Copyright (c) 2010-2013 NVIDIA Corporation
3 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clock.h>
30 #include <asm/arch/pinmux.h>
31 #include <asm/arch-tegra/clk_rst.h>
32 #include <asm/arch-tegra20/tegra20_sflash.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #define SPI_CMD_GO (1 << 30)
39 #define SPI_CMD_ACTIVE_SCLK_SHIFT 26
40 #define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
41 #define SPI_CMD_CK_SDA (1 << 21)
42 #define SPI_CMD_ACTIVE_SDA_SHIFT 18
43 #define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
44 #define SPI_CMD_CS_POL (1 << 16)
45 #define SPI_CMD_TXEN (1 << 15)
46 #define SPI_CMD_RXEN (1 << 14)
47 #define SPI_CMD_CS_VAL (1 << 13)
48 #define SPI_CMD_CS_SOFT (1 << 12)
49 #define SPI_CMD_CS_DELAY (1 << 9)
50 #define SPI_CMD_CS3_EN (1 << 8)
51 #define SPI_CMD_CS2_EN (1 << 7)
52 #define SPI_CMD_CS1_EN (1 << 6)
53 #define SPI_CMD_CS0_EN (1 << 5)
54 #define SPI_CMD_BIT_LENGTH (1 << 4)
55 #define SPI_CMD_BIT_LENGTH_MASK 0x0000001F
57 #define SPI_STAT_BSY (1 << 31)
58 #define SPI_STAT_RDY (1 << 30)
59 #define SPI_STAT_RXF_FLUSH (1 << 29)
60 #define SPI_STAT_TXF_FLUSH (1 << 28)
61 #define SPI_STAT_RXF_UNR (1 << 27)
62 #define SPI_STAT_TXF_OVF (1 << 26)
63 #define SPI_STAT_RXF_EMPTY (1 << 25)
64 #define SPI_STAT_RXF_FULL (1 << 24)
65 #define SPI_STAT_TXF_EMPTY (1 << 23)
66 #define SPI_STAT_TXF_FULL (1 << 22)
67 #define SPI_STAT_SEL_TXRX_N (1 << 16)
68 #define SPI_STAT_CUR_BLKCNT (1 << 15)
70 #define SPI_TIMEOUT 1000
71 #define TEGRA_SPI_MAX_FREQ 52000000
74 u32 command; /* SPI_COMMAND_0 register */
75 u32 status; /* SPI_STATUS_0 register */
76 u32 rx_cmp; /* SPI_RX_CMP_0 register */
77 u32 dma_ctl; /* SPI_DMA_CTL_0 register */
78 u32 tx_fifo; /* SPI_TX_FIFO_0 register */
79 u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
80 u32 rx_fifo; /* SPI_RX_FIFO_0 register */
83 struct tegra_spi_ctrl {
84 struct spi_regs *regs;
91 struct tegra_spi_slave {
92 struct spi_slave slave;
93 struct tegra_spi_ctrl *ctrl;
96 /* tegra20 only supports one SFLASH controller */
97 static struct tegra_spi_ctrl spi_ctrls[1];
99 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
101 return container_of(slave, struct tegra_spi_slave, slave);
104 int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs)
106 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
107 if (bus != 0 || cs != 0)
113 struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs,
114 unsigned int max_hz, unsigned int mode)
116 struct tegra_spi_slave *spi;
118 if (!spi_cs_is_valid(bus, cs)) {
119 printf("SPI error: unsupported bus %d / chip select %d\n",
124 if (max_hz > TEGRA_SPI_MAX_FREQ) {
125 printf("SPI error: unsupported frequency %d Hz. Max frequency"
126 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
130 spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
132 printf("SPI error: malloc of SPI structure failed\n");
135 spi->ctrl = &spi_ctrls[bus];
137 printf("SPI error: could not find controller for bus %d\n",
142 if (max_hz < spi->ctrl->freq) {
143 debug("%s: limiting frequency from %u to %u\n", __func__,
144 spi->ctrl->freq, max_hz);
145 spi->ctrl->freq = max_hz;
147 spi->ctrl->mode = mode;
152 void tegra20_spi_free_slave(struct spi_slave *slave)
154 struct tegra_spi_slave *spi = to_tegra_spi(slave);
159 int tegra20_spi_init(int *node_list, int count)
161 struct tegra_spi_ctrl *ctrl;
166 for (i = 0; i < count; i++) {
167 ctrl = &spi_ctrls[i];
170 ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
172 if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
173 debug("%s: no slink register found\n", __func__);
176 ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
177 "spi-max-frequency", 0);
179 debug("%s: no slink max frequency found\n", __func__);
183 ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
184 if (ctrl->periph_id == PERIPH_ID_NONE) {
185 debug("%s: could not decode periph id\n", __func__);
191 debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
192 __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
197 int tegra20_spi_claim_bus(struct spi_slave *slave)
199 struct tegra_spi_slave *spi = to_tegra_spi(slave);
200 struct spi_regs *regs = spi->ctrl->regs;
203 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
204 clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
207 /* Clear stale status here */
208 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
209 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
210 writel(reg, ®s->status);
211 debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
214 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
216 reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
217 if (spi->ctrl->mode & 2)
218 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
219 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
220 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
221 debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
224 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
227 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
228 pinmux_tristate_disable(PINGRP_LSPI);
229 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
234 void tegra20_spi_cs_activate(struct spi_slave *slave)
236 struct tegra_spi_slave *spi = to_tegra_spi(slave);
237 struct spi_regs *regs = spi->ctrl->regs;
239 /* CS is negated on Tegra, so drive a 1 to get a 0 */
240 setbits_le32(®s->command, SPI_CMD_CS_VAL);
243 void tegra20_spi_cs_deactivate(struct spi_slave *slave)
245 struct tegra_spi_slave *spi = to_tegra_spi(slave);
246 struct spi_regs *regs = spi->ctrl->regs;
248 /* CS is negated on Tegra, so drive a 0 to get a 1 */
249 clrbits_le32(®s->command, SPI_CMD_CS_VAL);
252 int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
253 const void *data_out, void *data_in, unsigned long flags)
255 struct tegra_spi_slave *spi = to_tegra_spi(slave);
256 struct spi_regs *regs = spi->ctrl->regs;
257 u32 reg, tmpdout, tmpdin = 0;
258 const u8 *dout = data_out;
263 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
264 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
267 num_bytes = bitlen / 8;
271 reg = readl(®s->status);
272 writel(reg, ®s->status); /* Clear all SPI events via R/W */
273 debug("spi_xfer entry: STATUS = %08x\n", reg);
275 reg = readl(®s->command);
276 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
277 writel(reg, ®s->command);
278 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
280 if (flags & SPI_XFER_BEGIN)
281 spi_cs_activate(slave);
283 /* handle data in 32-bit chunks */
284 while (num_bytes > 0) {
290 bytes = (num_bytes > 4) ? 4 : num_bytes;
293 for (i = 0; i < bytes; ++i)
294 tmpdout = (tmpdout << 8) | dout[i];
301 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
303 writel(tmpdout, ®s->tx_fifo);
304 setbits_le32(®s->command, SPI_CMD_GO);
307 * Wait for SPI transmit FIFO to empty, or to time out.
308 * The RX FIFO status will be read and cleared last
310 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
313 status = readl(®s->status);
315 /* We can exit when we've had both RX and TX activity */
316 if (is_read && (status & SPI_STAT_TXF_EMPTY))
319 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
323 else if (!(status & SPI_STAT_RXF_EMPTY)) {
324 tmpdin = readl(®s->rx_fifo);
327 /* swap bytes read in */
329 for (i = bytes - 1; i >= 0; --i) {
330 din[i] = tmpdin & 0xff;
338 if (tm >= SPI_TIMEOUT)
341 /* clear ACK RDY, etc. bits */
342 writel(readl(®s->status), ®s->status);
345 if (flags & SPI_XFER_END)
346 spi_cs_deactivate(slave);
348 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
349 tmpdin, readl(®s->status));
352 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);