2 * Copyright (c) 2010-2012 NVIDIA Corporation
3 * With help from the mpc8xxx SPI driver
4 * With more help from omap3_spi SPI driver
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/clock.h>
30 #include <asm/arch/pinmux.h>
31 #include <asm/arch/uart-spi-switch.h>
32 #include <asm/arch-tegra/clk_rst.h>
33 #include <asm/arch-tegra/tegra_spi.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_SPI_CORRUPTS_UART)
40 #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
42 #define corrupt_delay()
45 struct tegra_spi_slave {
46 struct spi_slave slave;
47 struct spi_tegra *regs;
53 static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
55 return container_of(slave, struct tegra_spi_slave, slave);
58 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
60 /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
61 if (bus != 0 || cs != 0)
67 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
68 unsigned int max_hz, unsigned int mode)
70 struct tegra_spi_slave *spi;
72 if (!spi_cs_is_valid(bus, cs)) {
73 printf("SPI error: unsupported bus %d / chip select %d\n",
78 if (max_hz > TEGRA_SPI_MAX_FREQ) {
79 printf("SPI error: unsupported frequency %d Hz. Max frequency"
80 " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
84 spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
86 printf("SPI error: malloc of SPI structure failed\n");
89 #ifdef CONFIG_OF_CONTROL
90 int node = fdtdec_next_compatible(gd->fdt_blob, 0,
91 COMPAT_NVIDIA_TEGRA20_SFLASH);
93 debug("%s: cannot locate sflash node\n", __func__);
96 if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
97 debug("%s: sflash is disabled\n", __func__);
100 spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
102 if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
103 debug("%s: no sflash register found\n", __func__);
106 spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
108 debug("%s: no sflash max frequency found\n", __func__);
111 spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
112 if (spi->periph_id == PERIPH_ID_NONE) {
113 debug("%s: could not decode periph id\n", __func__);
117 spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
118 spi->freq = TEGRA_SPI_MAX_FREQ;
119 spi->periph_id = PERIPH_ID_SPI1;
121 if (max_hz < spi->freq) {
122 debug("%s: limiting frequency from %u to %u\n", __func__,
126 debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
127 __func__, spi->regs, spi->freq, spi->periph_id);
133 void spi_free_slave(struct spi_slave *slave)
135 struct tegra_spi_slave *spi = to_tegra_spi(slave);
145 int spi_claim_bus(struct spi_slave *slave)
147 struct tegra_spi_slave *spi = to_tegra_spi(slave);
148 struct spi_tegra *regs = spi->regs;
151 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
152 clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
154 /* Clear stale status here */
155 reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
156 SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
157 writel(reg, ®s->status);
158 debug("spi_init: STATUS = %08x\n", readl(®s->status));
161 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
163 reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
165 reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
166 clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
167 SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
168 debug("spi_init: COMMAND = %08x\n", readl(®s->command));
171 * SPI pins on Tegra20 are muxed - change pinmux later due to UART
174 pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
175 pinmux_tristate_disable(PINGRP_LSPI);
177 #ifndef CONFIG_SPI_UART_SWITCH
180 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
181 * SPI UART switch or subsequent UART data won't go out! See
184 /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
189 void spi_release_bus(struct spi_slave *slave)
192 * We can't release UART_DISABLE and set pinmux to UART4 here since
193 * some code (e,g, spi_flash_probe) uses printf() while the SPI
194 * bus is held. That is arguably bad, but it has the advantage of
195 * already being in the source tree.
199 void spi_cs_activate(struct spi_slave *slave)
201 struct tegra_spi_slave *spi = to_tegra_spi(slave);
205 /* CS is negated on Tegra, so drive a 1 to get a 0 */
206 setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
208 corrupt_delay(); /* Let UART settle */
211 void spi_cs_deactivate(struct spi_slave *slave)
213 struct tegra_spi_slave *spi = to_tegra_spi(slave);
215 pinmux_select_uart();
217 /* CS is negated on Tegra, so drive a 0 to get a 1 */
218 clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
220 corrupt_delay(); /* Let SPI settle */
223 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
224 const void *data_out, void *data_in, unsigned long flags)
226 struct tegra_spi_slave *spi = to_tegra_spi(slave);
227 struct spi_tegra *regs = spi->regs;
228 u32 reg, tmpdout, tmpdin = 0;
229 const u8 *dout = data_out;
234 debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
235 slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
238 num_bytes = bitlen / 8;
242 reg = readl(®s->status);
243 writel(reg, ®s->status); /* Clear all SPI events via R/W */
244 debug("spi_xfer entry: STATUS = %08x\n", reg);
246 reg = readl(®s->command);
247 reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
248 writel(reg, ®s->command);
249 debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
251 if (flags & SPI_XFER_BEGIN)
252 spi_cs_activate(slave);
254 /* handle data in 32-bit chunks */
255 while (num_bytes > 0) {
261 bytes = (num_bytes > 4) ? 4 : num_bytes;
264 for (i = 0; i < bytes; ++i)
265 tmpdout = (tmpdout << 8) | dout[i];
272 clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
274 writel(tmpdout, ®s->tx_fifo);
275 setbits_le32(®s->command, SPI_CMD_GO);
278 * Wait for SPI transmit FIFO to empty, or to time out.
279 * The RX FIFO status will be read and cleared last
281 for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
284 status = readl(®s->status);
286 /* We can exit when we've had both RX and TX activity */
287 if (is_read && (status & SPI_STAT_TXF_EMPTY))
290 if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
294 else if (!(status & SPI_STAT_RXF_EMPTY)) {
295 tmpdin = readl(®s->rx_fifo);
298 /* swap bytes read in */
300 for (i = bytes - 1; i >= 0; --i) {
301 din[i] = tmpdin & 0xff;
309 if (tm >= SPI_TIMEOUT)
312 /* clear ACK RDY, etc. bits */
313 writel(readl(®s->status), ®s->status);
316 if (flags & SPI_XFER_END)
317 spi_cs_deactivate(slave);
319 debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
320 tmpdin, readl(®s->status));
323 printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);