4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
15 /* ti qpsi register bit masks */
16 #define QSPI_TIMEOUT 2000000
17 #define QSPI_FCLK 192000000
19 #define QSPI_CLK_EN (1 << 31)
20 #define QSPI_CLK_DIV_MAX 0xffff
22 #define QSPI_EN_CS(n) (n << 28)
23 #define QSPI_WLEN(n) ((n-1) << 19)
24 #define QSPI_3_PIN (1 << 18)
25 #define QSPI_RD_SNGL (1 << 16)
26 #define QSPI_WR_SNGL (2 << 16)
27 #define QSPI_INVAL (4 << 16)
28 #define QSPI_RD_QUAD (7 << 16)
30 #define QSPI_DD(m, n) (m << (3 + n*8))
31 #define QSPI_CKPHA(n) (1 << (2 + n*8))
32 #define QSPI_CSPOL(n) (1 << (1 + n*8))
33 #define QSPI_CKPOL(n) (1 << (n*8))
35 #define QSPI_WC (1 << 1)
36 #define QSPI_BUSY (1 << 0)
37 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
38 #define QSPI_XFER_DONE QSPI_WC
39 #define MM_SWITCH 0x01
41 #define MEM_CS_UNSELECT 0xfffff0ff
42 #define MMAP_START_ADDR 0x5c000000
43 #define CORE_CTRL_IO 0x4a002558
45 #define QSPI_CMD_READ (0x3 << 0)
46 #define QSPI_CMD_READ_QUAD (0x6b << 0)
47 #define QSPI_CMD_READ_FAST (0x0b << 0)
48 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
49 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
50 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
51 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
52 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
53 #define QSPI_CMD_WRITE (0x2 << 16)
54 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
56 /* ti qspi register set */
84 struct ti_qspi_slave {
85 struct spi_slave slave;
86 struct ti_qspi_regs *base;
92 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
94 return container_of(slave, struct ti_qspi_slave, slave);
97 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
99 struct spi_slave *slave = &qslave->slave;
102 slave->memory_map = (void *)MMAP_START_ADDR;
104 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
105 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
106 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
109 writel(memval, &qslave->base->setup0);
112 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
114 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
117 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
122 clk_div = (QSPI_FCLK / hz) - 1;
125 writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
126 &qslave->base->clk_ctrl);
128 /* assign clk_div values */
131 else if (clk_div > QSPI_CLK_DIV_MAX)
132 clk_div = QSPI_CLK_DIV_MAX;
135 writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
138 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
143 void spi_cs_activate(struct spi_slave *slave)
145 /* CS handled in xfer */
149 void spi_cs_deactivate(struct spi_slave *slave)
151 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
153 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
155 writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
163 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
164 unsigned int max_hz, unsigned int mode)
166 struct ti_qspi_slave *qslave;
168 qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
170 printf("SPI_error: Fail to allocate ti_qspi_slave\n");
174 qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
177 ti_spi_set_speed(&qslave->slave, max_hz);
179 #ifdef CONFIG_TI_SPI_MMAP
180 ti_spi_setup_spi_register(qslave);
183 return &qslave->slave;
186 void spi_free_slave(struct spi_slave *slave)
188 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
192 int spi_claim_bus(struct spi_slave *slave)
194 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
196 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
199 if (qslave->mode & SPI_CPHA)
200 qslave->dc |= QSPI_CKPHA(slave->cs);
201 if (qslave->mode & SPI_CPOL)
202 qslave->dc |= QSPI_CKPOL(slave->cs);
203 if (qslave->mode & SPI_CS_HIGH)
204 qslave->dc |= QSPI_CSPOL(slave->cs);
206 writel(qslave->dc, &qslave->base->dc);
207 writel(0, &qslave->base->cmd);
208 writel(0, &qslave->base->data);
213 void spi_release_bus(struct spi_slave *slave)
215 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
217 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
219 writel(0, &qslave->base->dc);
220 writel(0, &qslave->base->cmd);
221 writel(0, &qslave->base->data);
224 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
225 void *din, unsigned long flags)
227 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
228 uint words = bitlen >> 3; /* fixed 8-bit word length */
229 const uchar *txp = dout;
234 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
235 slave->bus, slave->cs, bitlen, words, flags);
237 /* Setup mmap flags */
238 if (flags & SPI_XFER_MMAP) {
239 writel(MM_SWITCH, &qslave->base->memswitch);
240 val = readl(CORE_CTRL_IO);
242 writel(val, CORE_CTRL_IO);
244 } else if (flags & SPI_XFER_MMAP_END) {
245 writel(~MM_SWITCH, &qslave->base->memswitch);
246 val = readl(CORE_CTRL_IO);
247 val &= MEM_CS_UNSELECT;
248 writel(val, CORE_CTRL_IO);
256 debug("spi_xfer: Non byte aligned SPI transfer\n");
260 /* Setup command reg */
262 qslave->cmd |= QSPI_WLEN(8);
263 qslave->cmd |= QSPI_EN_CS(slave->cs);
264 if (flags & SPI_3WIRE)
265 qslave->cmd |= QSPI_3_PIN;
266 qslave->cmd |= 0xfff;
270 debug("tx cmd %08x dc %08x data %02x\n",
271 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
272 writel(*txp++, &qslave->base->data);
273 writel(qslave->cmd | QSPI_WR_SNGL,
275 status = readl(&qslave->base->status);
276 timeout = QSPI_TIMEOUT;
277 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
279 printf("spi_xfer: TX timeout!\n");
282 status = readl(&qslave->base->status);
284 debug("tx done, status %08x\n", status);
287 qslave->cmd |= QSPI_RD_SNGL;
288 debug("rx cmd %08x dc %08x\n",
289 qslave->cmd, qslave->dc);
290 writel(qslave->cmd, &qslave->base->cmd);
291 status = readl(&qslave->base->status);
292 timeout = QSPI_TIMEOUT;
293 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
295 printf("spi_xfer: RX timeout!\n");
298 status = readl(&qslave->base->status);
300 *rxp++ = readl(&qslave->base->data);
301 debug("rx done, status %08x, read %02x\n",
306 /* Terminate frame */
307 if (flags & SPI_XFER_END)
308 spi_cs_deactivate(slave);