4 * Copyright (C) 2013, Texas Instruments, Incorporated
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/omap.h>
15 #include <asm/omap_gpio.h>
17 /* ti qpsi register bit masks */
18 #define QSPI_TIMEOUT 2000000
19 #define QSPI_FCLK 192000000
21 #define QSPI_CLK_EN (1 << 31)
22 #define QSPI_CLK_DIV_MAX 0xffff
24 #define QSPI_EN_CS(n) (n << 28)
25 #define QSPI_WLEN(n) ((n-1) << 19)
26 #define QSPI_3_PIN (1 << 18)
27 #define QSPI_RD_SNGL (1 << 16)
28 #define QSPI_WR_SNGL (2 << 16)
29 #define QSPI_INVAL (4 << 16)
30 #define QSPI_RD_QUAD (7 << 16)
32 #define QSPI_DD(m, n) (m << (3 + n*8))
33 #define QSPI_CKPHA(n) (1 << (2 + n*8))
34 #define QSPI_CSPOL(n) (1 << (1 + n*8))
35 #define QSPI_CKPOL(n) (1 << (n*8))
37 #define QSPI_WC (1 << 1)
38 #define QSPI_BUSY (1 << 0)
39 #define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
40 #define QSPI_XFER_DONE QSPI_WC
41 #define MM_SWITCH 0x01
43 #define MEM_CS_UNSELECT 0xfffff0ff
44 #define MMAP_START_ADDR_DRA 0x5c000000
45 #define MMAP_START_ADDR_AM43x 0x30000000
46 #define CORE_CTRL_IO 0x4a002558
48 #define QSPI_CMD_READ (0x3 << 0)
49 #define QSPI_CMD_READ_QUAD (0x6b << 0)
50 #define QSPI_CMD_READ_FAST (0x0b << 0)
51 #define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
52 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
53 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
54 #define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
55 #define QSPI_SETUP0_READ_QUAD (0x3 << 12)
56 #define QSPI_CMD_WRITE (0x2 << 16)
57 #define QSPI_NUM_DUMMY_BITS (0x0 << 24)
59 /* ti qspi register set */
87 struct ti_qspi_slave {
88 struct spi_slave slave;
89 struct ti_qspi_regs *base;
95 static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
97 return container_of(slave, struct ti_qspi_slave, slave);
100 static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
102 struct spi_slave *slave = &qslave->slave;
106 slave->memory_map = (void *)MMAP_START_ADDR_DRA;
108 slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
111 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
112 QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
113 QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
116 writel(memval, &qslave->base->setup0);
119 static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
121 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
124 debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
129 clk_div = (QSPI_FCLK / hz) - 1;
132 writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
133 &qslave->base->clk_ctrl);
135 /* assign clk_div values */
138 else if (clk_div > QSPI_CLK_DIV_MAX)
139 clk_div = QSPI_CLK_DIV_MAX;
142 writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
145 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
150 void spi_cs_activate(struct spi_slave *slave)
152 /* CS handled in xfer */
156 void spi_cs_deactivate(struct spi_slave *slave)
158 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
160 debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
162 writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
170 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
171 unsigned int max_hz, unsigned int mode)
173 struct ti_qspi_slave *qslave;
176 gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
177 gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
180 qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
182 printf("SPI_error: Fail to allocate ti_qspi_slave\n");
186 qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
189 ti_spi_set_speed(&qslave->slave, max_hz);
191 #ifdef CONFIG_TI_SPI_MMAP
192 ti_spi_setup_spi_register(qslave);
195 return &qslave->slave;
198 void spi_free_slave(struct spi_slave *slave)
200 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
204 int spi_claim_bus(struct spi_slave *slave)
206 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
208 debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
211 if (qslave->mode & SPI_CPHA)
212 qslave->dc |= QSPI_CKPHA(slave->cs);
213 if (qslave->mode & SPI_CPOL)
214 qslave->dc |= QSPI_CKPOL(slave->cs);
215 if (qslave->mode & SPI_CS_HIGH)
216 qslave->dc |= QSPI_CSPOL(slave->cs);
218 writel(qslave->dc, &qslave->base->dc);
219 writel(0, &qslave->base->cmd);
220 writel(0, &qslave->base->data);
225 void spi_release_bus(struct spi_slave *slave)
227 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
229 debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
231 writel(0, &qslave->base->dc);
232 writel(0, &qslave->base->cmd);
233 writel(0, &qslave->base->data);
236 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
237 void *din, unsigned long flags)
239 struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
240 uint words = bitlen >> 3; /* fixed 8-bit word length */
241 const uchar *txp = dout;
250 debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
251 slave->bus, slave->cs, bitlen, words, flags);
253 /* Setup mmap flags */
254 if (flags & SPI_XFER_MMAP) {
255 writel(MM_SWITCH, &qslave->base->memswitch);
257 val = readl(CORE_CTRL_IO);
259 writel(val, CORE_CTRL_IO);
262 } else if (flags & SPI_XFER_MMAP_END) {
263 writel(~MM_SWITCH, &qslave->base->memswitch);
265 val = readl(CORE_CTRL_IO);
266 val &= MEM_CS_UNSELECT;
267 writel(val, CORE_CTRL_IO);
276 debug("spi_xfer: Non byte aligned SPI transfer\n");
280 /* Setup command reg */
282 qslave->cmd |= QSPI_WLEN(8);
283 qslave->cmd |= QSPI_EN_CS(slave->cs);
284 if (flags & SPI_3WIRE)
285 qslave->cmd |= QSPI_3_PIN;
286 qslave->cmd |= 0xfff;
288 /* FIXME: This delay is required for successfull
289 * completion of read/write/erase. Once its root
290 * caused, it will be remove from the driver.
297 debug("tx cmd %08x dc %08x data %02x\n",
298 qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
299 writel(*txp++, &qslave->base->data);
300 writel(qslave->cmd | QSPI_WR_SNGL,
302 status = readl(&qslave->base->status);
303 timeout = QSPI_TIMEOUT;
304 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
306 printf("spi_xfer: TX timeout!\n");
309 status = readl(&qslave->base->status);
311 debug("tx done, status %08x\n", status);
314 qslave->cmd |= QSPI_RD_SNGL;
315 debug("rx cmd %08x dc %08x\n",
316 qslave->cmd, qslave->dc);
320 writel(qslave->cmd, &qslave->base->cmd);
321 status = readl(&qslave->base->status);
322 timeout = QSPI_TIMEOUT;
323 while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
325 printf("spi_xfer: RX timeout!\n");
328 status = readl(&qslave->base->status);
330 *rxp++ = readl(&qslave->base->data);
331 debug("rx done, status %08x, read %02x\n",
336 /* Terminate frame */
337 if (flags & SPI_XFER_END)
338 spi_cs_deactivate(slave);